Claims
- 1. A method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate which lies in an x-y plane, said method comprising the steps of:forming a semiconductive structure having an active surface and insulatively disposed over a semiconductor substrate; amorphizing a portion of said active surface of said semiconductive structure by introducing an amorphizing substance into said active surface of said semiconductive structure at an angle, theta, which is greater than seven degrees from a z-axis which is normal to the semiconductive structure active surface and at an angle capable of introduction into said surface; then forming a metal layer on said active surface of said semiconductive structure; and forming a lower resistivity silicide on said semiconductive structure by interacting said metal layer with said semiconductive structure in said amorphized portion of said semiconductive structure.
- 2. The method of claim 1, wherein said semiconductive structure is comprised of a material selected from the group consisting of: doped polysilicon, undoped polysilicon, epitaxial silicon, and any combination thereof.
- 3. The method of claim 1, wherein said metal layer is comprised of a material selected from the group consisting of: titanium, Co, W, Mo, nickel, platinum, palladium, and any combination thereof.
- 4. The method of claim 1, further comprising the step of performing a low temperature anneal step after said step of forming a metal layer on said gate structure.
- 5. The method of claim 4, wherein said low temperature anneal step is comprised of subjecting said transistor to temperatures in excess of 600 C.
- 6. The method of claim 4, wherein said low temperature anneal step is comprised of subjecting said transistor to a temperature around 700 to 800 C.
- 7. The method of claim 1, wherein said amorphizing substance is comprised of a substance selected from the group consisting of: As, Ge, or any combination thereof.
- 8. A method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate which lies in an x-y plane and has a gate length, said method comprising the steps of:forming a semiconductive structure having a thickness insulatively disposed over a semiconductor substrate; amorphizing a portion of said semiconductive structure by introducing an amorphizing substance into said semiconductive structure at an angle, theta, which is greater than seven degrees from a z-axis which is normal to the semiconductor substrate; forming a metal layer on said semiconductive structure; and wherein said metal layer interacts with said semiconductive structure in said amorphized portion of said semiconductive structure so as to form a lower resistivity silicide on said semiconductive structure; wherein said angle, theta, is determined by: theta>arctan (L/d) where L is the gate length of said transistor and d is the thickness of the semiconductive structure.
- 9. A method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate which lies in an x-y plane in an integrated circuit having at least one other gate structure at a distance from said silicided gate structure said silicided gate structure and said other gate structure having edges, said method comprising the steps of:forming a semiconductive structure insulatively disposed over a semiconductor substrate; amorphizing a portion of said semiconductive structure by introducing an amorphizing substance into said semiconductive structure at an angle, theta, which is greater than seven degrees from a z-axis which is normal to the semiconductor substrate; forming a metal layer on said semiconductive structure; and wherein said metal layer interacts with said semiconductive structure in said amorphized portion of said semiconductive structure so as to form a lower resistivity silicide on said semiconductive structure; wherein said angle, theta, is determined by: 7°<theta arctan≦(L′/d) where L′ is the shortest distance from an edge of one gate structure to an edge of the closest gate structure plus the height of the underlying gate insulator and d is the thickness of the semiconductive structure.
- 10. The method of claim 1, wherein said angle, theta, is around 25 degrees.
- 11. The method of claim 1, wherein said semiconductor substrate is rotated in the x-y plane during said step of introducing said amorphizing substance into said semiconductor structure.
- 12. The method of claim 11, wherein said semiconductor substrate is continuously rotated in the x-y plane during said step of introducing said amorphizing substance into said semiconductor structure.
- 13. The method of claim 11, wherein said semiconductor substrate is rotated in discrete steps in the x-y plane during said step of introducing said amorphizing substance into said semiconductor structure, said discrete steps having a step size.
- 14. The method of claim 13, wherein said step size is around 90 degrees.
- 15. The method of claim 13, wherein said step size is around 45 degrees.
- 16. A method of siliciding a structure comprised of a semiconductive material having an active surface situated over a semiconductor substrate, said method comprising the steps of:providing a semiconductive material having an active surface over a semiconductor substrate; amorphizing a portion of said semiconductive material by introducing an amorphizing substance into said semiconductive material at an angle, theta, which is greater than seven degrees from a z-axis which is normal to said semiconductive material active surface and at an angle capable of introduction into said semiconductor material active surface forming a metal layer on said semiconductive material; and said metal layer forming a silicide on said semiconductive material by interacting with said semiconductive material in the amorphized portion of said semiconductive material.
- 17. The method of claim 16, wherein said semiconductive structure is comprised of a material selected from the group consisting of: doped polysilicon, undoped polysilicon, epitaxial silicon, and any combination thereof.
- 18. The method of claim 16, wherein said metal layer is comprised of a material selected from the group consisting of: titanium, Co, W, Mo, nickel, platinum, palladium, and any combination thereof.
- 19. The method of claim 16, wherein said amorphizing substance is comprised of a substance selected from the group consisting of: As, Ge, or any combination thereof.
- 20. A method of siliciding a structure comprised of a semiconductive material situated over a semiconductor substrate, said method comprising the steps of:amorphizing a portion of said semiconductive material by introducing an amorphizing substance into said semiconductive material at an angle, theta, which is greater than seven degrees from a z-axis which is normal to said semiconductive substrate; forming a metal layer on said semiconductive material; and wherein said metal layer interacts with said semiconductive material in the amorphized portion of said semiconductive material so as to form a silicide on said semiconductive material. wherein said angle, theta, is determined by: 7°<theta arctan≦(L′/d) where L′ is the shortest distance from an edge of one structure to an edge of the closest structure and d is the height of the semiconductive material.
CROSS-REFERENCE TO RELATED PATENT/PATENT APPLICATIONS
This application claims priority under 35 USC §1 19(e)(1) of provisional application No. 60/084,474 filed May 6, 1998.
The following commonly assigned patent/patent applications are hereby incorporated herein by reference:
The above noted applications were filed and claim priority based upon provisional applications Serial No. 60/048,143, filed May 30, 1997, Serial No. 60/051,725, filed Jul. 3, 1997 and Serial No. 60/084,816, filed May 8, 1998, respectively.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
4943728 |
Dykstra et al. |
Jul 1990 |
|
5223445 |
Fuse |
Jun 1993 |
|
Non-Patent Literature Citations (2)
Entry |
H. Ito, M. Sasaki, N. Kimizuka, J. Uwasawa, N. Nakamura, T. Ito, Y. Goto, A. Tsuboi, S. Watanuki, T. Ueda, and T. Horiuchi, Gate Electrode Microstructure Having Stacked Large-Grain Poly-Si with Ultra-Thin SiOx Interlayer for Reliability in Sub-Micrometer CMOS. IEDM 97-635. 0-7803-4100-7/97. IEEE. pp. 26.3.1-26.3-4. |
Jiunn-Yann Tsai, Stanley W.-C. Yeh. Device Degradation Associated with Pre-Amorphization Implant (PAI) of the Ti Salicide Process. 1997 International Symposium on VLSI Technology, Systems, and Applications, Proceedings of Technical Papers, Jun. 3-5, 1997, pp. 28-33. |
Provisional Applications (1)
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Number |
Date |
Country |
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60/084474 |
May 1998 |
US |