Claims
- 1. A flash memory semiconductor apparatus, said apparatus comprising:
a. a semiconductor substrate; b. at least one region on said substrate member having a silicon dioxide layer; c. a silicon material deposited over said silicon dioxide layer, said silicon material and said silicon dioxide layer being formed into at least one partial stack portion of a flash memory element, said silicon material formed into said at least one stack portion comprising a first polysilicon layer of said flash memory element; d. a pre-interpoly dielectric treatment layer, said pre-interpoly dielectric treatment layer being formed over said first polysilicon layer; e. an interpoly dielectric member, said interpoly dielectric member being formed over said pre-interpoly dielectric treatment layer; and f. a second polysilicon layer, said second polysilicon layer being formed over said interpoly dielectric member and forming another fabricated stage of said flash memory element.
- 2. A flash memory semiconductor apparatus, as recited in claim 1, wherein:
a. said pre-interpoly dielectric treatment layer comprises a solid material produced from a chemical reaction in a batch furnace, said chemical reaction comprises treating said first polysilicon layer in said batch furnace at an elevated temperature ranging from 800° C. to 1050° C. for a duration ranging from one (1) minute to two (2) hours in a gas mixture, and b. said gas mixture comprising at least one reagent gas selected from a group of reagent gases consisting essentially of a nitric oxide (NO) and a nitrous oxide (N2O), in a concentration ranging from 5 to 100 volume %, and at least one diluent gas selected from a group of diluent gases consisting essentially of argon (Ar), nitrogen (N2), and oxygen (O2), in a concentration balancing that of the selected at least one reagent gas, at a pressure ranging from 0.1 to 10.0 atmospheres.
- 3. A flash memory semiconductor apparatus, as recited in claim 1, wherein:
a. said pre-interpoly dielectric treatment layer comprises a solid material produced from a chemical reaction in a single wafer RTA tool, said chemical reaction comprises treating said first polysilicon layer in said RTA tool at an elevated temperature ranging from 700° C. to 1150° C. for a duration ranging from one (1) second to two (2) minutes in a gas mixture, and b. said gas mixture comprising at least one reagent gas selected from a group of reagent gases consisting essentially of nitric oxide (NO) and nitrous oxide (N2O), in a concentration ranging from 1 to 100 volume %, and at least one diluent gas selected from a group of diluent gases consisting essentially of argon (Ar), nitrogen (N2), and oxygen (O2), in a concentration balancing that of the selected at least one reagent gas.
- 4. A flash memory semiconductor apparatus, as recited in claim 1, wherein:
said pre-interpoly dielectric treatment layer comprises a solid material produced from a chemical reaction in a plasma chamber, said chemical reaction comprises treating a surface of said first polysilicon layer in a plasma for a duration ranging from one (1) second to two (2) minutes, said plasma being selected from a plasma group of reagent gases consisting essentially of nitric oxide (NO) plasma and nitrous oxide (N2O) plasma.
- 5. A flash memory semiconductor apparatus, as recited in claim 1, wherein:
a. said pre-interpoly dielectric treatment layer comprises a solid material produced from a chemical reaction in a batch furnace, said chemical reaction comprises treating said first polysilicon layer in said batch furnace at an elevated temperature ranging from 800° C. to 1050° C. for a duration ranging from one (1) minute to sixty (60) minutes in a gas mixture, and b. said gas mixture comprising at least one reagent gas selected from a group of reagent gases consisting essentially of oxygen (O2) and water (H2O), in a concentration ranging from 5 to 100 volume %, and at least one diluent gas selected from a group of diluent gases consisting essentially of argon (Ar) and nitrogen (N2), in a concentration balancing that of the selected at least one reagent gas, at a pressure ranging from 0.5 to 10.0 atmospheres.
- 6. A flash memory semiconductor apparatus, as recited in claim 1, wherein:
a. said pre-interpoly dielectric treatment layer comprises a solid material produced from a chemical reaction in a single wafer RTA tool, said chemical reaction comprises treating said first polysilicon layer in said RTA tool at an elevated temperature ranging from 700° C. to 1150° C. for a duration ranging from one (1) second to one hundred twenty seconds with a gas mixture, and b. said gas mixture comprising at least one ambient reagent gas selected from a group of reagent gases consisting essentially of oxygen (O2) and water (H2O), in a concentration ranging from 1 to 100 volume % and 0.5 to 80 volume percent, respectively, and at least one diluent gas selected from a group of diluent gases consisting essentially of argon (Ar) and nitrogen (N2), in a concentration balancing that of the selected at least one reagent gas.
- 7. A flash memory semiconductor apparatus, as recited in claim 1, wherein:
a. said pre-interpoly dielectric treatment layer comprises a solid material produced from a chemical reaction in a batch furnace, said chemical reaction comprises treating said first polysilicon layer in said batch furnace at an elevated temperature ranging from 800° C. to 1050° C. for a duration ranging from one (1) minute to one hundred twenty (120) minutes in a gas mixture, and said gas mixture comprising a reagent gas, ammonia (NH3), in a concentration ranging from 5 to 100 volume %, and at least one diluent gas selected from a group of diluent gases consisting essentially of argon (Ar) and nitrogen (N2), in a concentration balancing that of the selected at least one reagent gas, at a pressure ranging from 0.5 to 10.0 atmospheres.
- 8. A flash memory semiconductor apparatus, as recited in claim 1, wherein:
a. said pre-interpoly dielectric treatment layer comprises a solid material produced from a chemical reaction in a single wafer RTA tool, said chemical reaction comprises treating said first polysilicon layer in said RTA tool at an elevated temperature ranging from 700° C. to 1150° C. for a duration ranging from one (1) second to one hundred twenty (120) seconds in a gas mixture, and b. said gas mixture comprising a reagent gas, ammonia (NH3), in a concentration ranging from 5 to 100 volume %, and at least one diluent gas stream selected from a group of diluent gases consisting essentially of argon (Ar) and nitrogen (N2), in a concentration balancing that of the selected at least one reagent gas.
- 9. A flash memory semiconductor apparatus, as recited in claim 1, wherein:
said pre-interpoly dielectric treatment layer comprises a solid material produced from a chemical reaction in a plasma chamber, said chemical reaction comprises treating a surface of said first polysilicon layer in a reagent gas, ammonia (NH3), plasma for a duration ranging from one (1) second to two (2) minutes.
- 10. A method of fabricating a flash memory semiconductor apparatus, said method comprising the steps of:
a. providing a semiconductor substrate; b. fabricating a silicon dioxide layer on at least one region of said substrate member; c. depositing a silicon material over said silicon dioxide layer; d. forming said silicon material and said silicon dioxide layer into at least one partial stack portion of a flash memory element, said silicon material formed into said at least one stack portion comprising a first polysilicon layer of said flash memory element; e. forming a pre-interpoly dielectric treatment layer over said first polysilicon layer; f. forming an interpoly dielectric member over said pre-interpoly dielectric treatment layer; and forming a second polysilicon layer over said interpoly dielectric member.
- 11. A method of fabricating a flash memory semiconductor apparatus, as recited in claim 10, wherein:
a. said step of forming a pre-interpoly dielectric treatment layer over said first polysilicon layer comprises producing a solid material by a chemical reaction in a batch furnace, said chemical reaction comprises treating said first polysilicon layer in said batch furnace by heating said polysilicon layer to an elevated temperature ranging from 800° C. to 1050° C. for a duration ranging from one (1) minute to two (2) hours, exposing said heated first polysilicon layer to a gas mixture, and b. said gas mixture comprising at least one reagent gas selected from a group of reagent gases consisting essentially of a nitric oxide (NO) and a nitrous oxide (N2O), in a concentration ranging from 5 to 100 volume %, and at least one diluent gas selected from a group of diluent gases consisting essentially of argon (Ar), nitrogen (N2), and oxygen (O2), in a concentration balancing that of the selected at least one reagent gas, and pressurizing said batch furnace to a pressure ranging from 0.1 to 10.0 atmospheres.
- 12. A method of fabricating a flash memory semiconductor apparatus, as recited in claim 10, wherein:
a. said step of forming a pre-interpoly dielectric treatment layer over said first polysilicon layer comprises producing a solid material by a chemical reaction in a single wafer RTA tool, said chemical reaction comprises treating said first polysilicon layer in said RTA tool by heating said polysilicon layer to an elevated temperature ranging from 700° C. to 1150° C. for a duration ranging from one (1) second to two (2) minutes, exposing said heated first polysilicon layer to a gas mixture, and b. said gas mixture comprising at least one reagent gas selected from a group of reagent gases consisting essentially of a nitric oxide (NO) and a nitrous oxide (N2O), in a concentration ranging from 5 to 100 volume %, and at least one diluent gas selected from a group of diluent gases consisting essentially of argon (Ar), nitrogen (N2), and oxygen (O2), in a concentration balancing that of the selected at least one reagent gas.
- 13. A method of fabricating a flash memory semiconductor apparatus, as recited in claim 10, wherein:
said step of forming pre-interpoly dielectric treatment layer over said first polysilicon layer comprises producing a solid material by a chemical reaction in a plasma chamber, said chemical reaction comprises treating a surface of said first polysilicon layer in a plasma for a duration ranging from one (1) second to two (2) minutes, said plasma being selected from a plasma group consisting of a nitrogen (N2) plasma and a nitrous oxide (N2O) plasma.
- 14. A method of fabricating a flash memory semiconductor apparatus, as recited in claim 10, wherein:
a. said step of forming a pre-interpoly dielectric treatment layer over said first polysilicon layer comprises producing a solid material by a chemical reaction in a batch furnace, said chemical reaction comprises treating said first polysilicon layer in said batch furnace by heating said first polysilicon layer to an elevated temperature ranging from 800° C. to 1050° C. for a duration ranging from one (1) minute to sixty minutes, exposing said heated first polysilicon layer to in a gas mixture, and b. said gas mixture comprising at least one reagent gas selected from a group of reagent gases consisting essentially of oxygen (O2) and water (H2O), in a concentration ranging from 5 to 100 volume %, and at least one diluent gas selected from a group of diluent gases consisting essentially of argon (Ar) and nitrogen (N2), in a concentration balancing that of the selected at least one reagent gas, and pressurizing said batch furnace to a pressure ranging from 0.5 to 10.0 atmospheres.
- 15. A method of fabricating a flash memory semiconductor apparatus, as recited in claim 10, wherein:
a. said step of forming a pre-interpoly dielectric treatment layer over said first polysilicon layer comprises producing a solid material by a chemical reaction in a single wafer RTA tool, said chemical reaction comprises treating said first polysilicon layer in said RTA tool at an elevated temperature ranging from 700° C. to 1150° C. for a duration ranging from one (1) second to one hundred twenty (120) seconds, exposing said heated first polysilicon layer to a gas mixture, and b. said gas mixture comprising at least one ambient reagent gas selected from a group of reagent gases consisting essentially of oxygen (O2) and water (H2O), in a concentration ranging from 1 to 100 volume % and 0.5 to 80 volume percent, respectively, and at least one diluent gas selected from a group of diluent gases consisting essentially of argon (Ar) and nitrogen (N2), in a concentration balancing that of the selected at least one reagent gas.
- 16. A method of fabricating a flash memory semiconductor apparatus, as recited in claim 10, wherein:
a. said step of forming a pre-interpoly dielectric treatment layer over said first polysilicon layer comprises producing a solid material by a chemical reaction in a batch furnace, said chemical reaction comprises treating said first polysilicon layer in said batch furnace by heating said first polysilicon layer to an elevated temperature ranging from 800° C. to 1050° C. for a duration ranging from one (1) minute to one hundred twenty (120) minutes, exposing said heated first polysilicon layer to a gas mixture, b. said gas mixture comprising a reagent gas, ammonia (NH3), in a concentration ranging from 5 to 100 volume %, and at least one diluent gas stream selected from a group of diluent gases consisting essentially of argon (Ar) and nitrogen (N2), in a concentration balancing that of the selected at least one reagent gas, and pressurizing said batch furnace to a pressure ranging from 0.5 to 10.0 atmospheres.
- 17. A method of fabricating a flash memory semiconductor apparatus, as recited in claim 10, wherein:
a. said step of forming a pre-interpoly dielectric treatment layer over said first polysilicon layer comprises producing a solid material by a chemical reaction in a single wafer RTA tool, said chemical reaction comprises treating said first polysilicon layer in said RTA tool by heating said first polysilicon layer to an elevated temperature ranging from 700° C. to 1150° C. for a duration ranging from one (1) second to one hundred twenty (120) seconds, exposing said heated first polysilicon layer to a gaseous mix, b. said gas mixture comprising a reagent gas, ammonia (NH3), in a concentration ranging from 1 to 100 volume %, and at least one diluent gas stream selected from a group of diluent gases consisting essentially of argon (Ar) and nitrogen (N2), in a concentration balancing that of the selected at least one reagent gas.
- 18. A method of fabricating a flash memory semiconductor apparatus as recited in claim 10, wherein:
said step of forming a pre-interpoly dielectric treatment layer over said first polysilicon layer comprises producing a solid material by a chemical reaction in a plasma chamber, said chemical reaction comprises treating a surface of said first polysilicon layer in a reagent gas plasma, ammonia (NH3), for a duration ranging from one (1) second to two (2) minutes.
- 19. A flash memory semiconductor apparatus, said apparatus comprising:
a. a semiconductor substrate; b. at least one region on said substrate member having a silicon dioxide layer; c. a silicon material deposited over said silicon dioxide layer, said silicon material and said silicon dioxide layer being formed into at least one partial stack portion of a flash memory element, said silicon material formed into said at least one stack portion comprising a first polysilicon layer of said flash memory element; d. a pre-interpoly dielectric treatment layer, said pre-interpoly dielectric treatment layer being formed over said first polysilicon layer; e. a multi-layered interpoly dielectric member, said multi-layered interpoly dielectric member being formed such that said pre-interpoly dielectric treatment layer facilitates a thickness decrease ranging from 5 to 30 Å for said dielectric member, thereby increasing a capacitor coupling ratio from 5% to 10% and lowering a power supply programming voltage by 2 to 10%; and f. a second polysilicon layer, said second polysilicon layer being formed over said interpoly dielectric member and forming another fabricated stage of said flash memory element.
- 20. A flash memory semiconductor apparatus, as recited in claim 19 wherein:
said multi-layered interpoly dielectric member comprises
a. a top oxide layer of silicon dioxide; b. a middle nitride layer of silicon nitride; and c. a bottom oxide layer of silicon dioxide, and said multi-layered interpoly dielectric member being known as an ONO.
RELATED APPLICATION
[0001] This application is related to co-pending U.S. Provisional Patent Application Ser. No. 60/148,899, entitled “FLASH MEMORY HAVING PRE-INTERPOLY DIELECTRIC TREATMENT LAYER AND METHOD OF FORMING,” filed Aug. 13, 1999, by the same Applicants.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60148899 |
Aug 1999 |
US |
Divisions (1)
|
Number |
Date |
Country |
Parent |
09594207 |
Jun 2000 |
US |
Child |
10291293 |
Nov 2002 |
US |