Claims
- 1. A method of forming interconnects having different resistances in a semiconductor device, comprising:
- forming a first layer of a conductive material for a plurality of interconnects, said first layer of conductive material for each of said plurality of interconnects in ohmic contact with a conductive region through an interconnect hole in an interlayer dielectric overlying the conductive region;
- forming a second layer of material overlying and in ohmic contact with said first layer of material, said second layer of material comprising a metal that is chemically convertible to a material more resistive than said first layer of material;
- chemically converting said metal to a material more resistive than said first layer of material;
- forming a third layer of a material overlying and in ohmic contact with said second layer of material, said third layer of material being more conductive than said chemically converted second layer material;
- masking a region of said third layer overlying one or more interconnects which are desired to have a high resistance; and
- removing unmasked portions of said second and third layers.
- 2. The method of claim 1, further comprising removing said mask and cleaning any unwanted material from the interconnects.
- 3. The method of claim 1, wherein the chemically converted second layer increases the resistance of the one or more higher resistance interconnects to from about 10 k.OMEGA. to 10 G.OMEGA..
- 4. The method of claim 1, wherein the chemically converted second layer increases the resistance of the one or more higher resistance interconnects to from about 1 G.OMEGA. to 10 G.OMEGA..
- 5. The method of claim 1, wherein the second layer of material comprises TiN and said chemical conversion is achieved by oxidation.
- 6. The method of claim 5, wherein the oxidation of said TiN layer is achieved by a furnace anneal.
- 7. The method of claim 6, wherein said furnace anneal comprises N.sub.2 and O.sub.2 flow controlled to consume all of the TiN layer.
- 8. The method of claim 1, wherein said third layer of material comprises TiN.
- 9. The method of claim 1, wherein said first layer of conductive material comprises tungsten.
- 10. The method of claim 1, wherein at least one of said one or more higher resistance interconnects provides a contact between a doped silicon region and a metal region separated by said interlayer dielectric.
- 11. The method of claim 10, wherein said doped silicon region is a source/drain region of a NMOS transistor.
- 12. The method of claim 1, wherein at least one of said one or more higher resistance interconnects provides a via between a metal region and a second metal region separated by said interlayer dielectric.
- 13. A method of forming interconnects having different resistances in a semiconductor device, comprising:
- forming a layer of TiN over a plurality of interconnects formed in an interlayer dielectric;
- oxidizing said layer of TiN;
- forming a second layer of TiN over said oxidized layer of TiN;
- masking a region of said second TiN layer overlying one or more interconnects which are desired to have a higher resistance; and
- removing unmasked oxidized TiN and TiN layers.
- 14. The method of claim 13, further comprising removing said mask and cleaning any oxidized material from the interconnects which are desired to have lower resistance.
- 15. The method of claim 13, wherein the oxidized TiN layer increases the resistance of said one or more higher resistance interconnects to from about 10 k.OMEGA. to 10 G.OMEGA..
- 16. The method of claim 13, wherein the oxidized TiN layer increases the resistance of said one or more higher resistance interconnects to from about 1 G.OMEGA. to 10 G.OMEGA..
- 17. The method of claim 13, wherein the first formed TiN layer has a thickness of from about 10 to 200 .ANG..
- 18. The method of claim 13, wherein the second formed TiN layer has a thickness of from about 500 .ANG. to 1 k.ANG..
- 19. The method of claim 13, wherein the oxidation of said first formed TiN layer is achieved by a furnace anneal.
- 20. The method of claim 19, wherein said furnace anneal comprises N.sub.2 and O.sub.2 flow controlled to consume all of the first formed TiN layer.
- 21. The method of claim 13, wherein at least one of said one or more interconnects comprises tungsten.
- 22. The method of claim 14, further comprising forming and patterning a metal layer overlying and in ohmic contact with one or more of said plurality of interconnects.
- 23. The method of claim 13, wherein at least one of the one or more higher resistance interconnects provides a contact between a doped silicon region and a metal region separated by said interlayer dielectric.
- 24. The method of claim 22, wherein said doped silicon region is a source/drain region of a NMOS transistor.
- 25. The method of claim 13, wherein at least one of the one or more higher resistance interconnects provides a via between a metal region and a second metal region separated by said interlayer dielectric.
- 26. The method of claim 2, further comprising forming and patterning a metal layer overlying and in ohmic contact with one or more of said plurality of interconnects.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of the filing date of Provisional Application Ser. No. 60/087,108, entitled HIGHLY RESISTIVE CONTACTS, filed May 28, 1998.
US Referenced Citations (8)