Claims
- 1. A semiconductor device, comprising:a silicon substrate; and a MOM capacitor formed on said silicon substrate, including; a first electrode layer formed on said silicon substrate; a metal silicide located between said first electrode and said silicon substrate and formed from a first portion of said first metal electrode layer; a metal oxide layer formed from said first metal electrode layer, said metal oxide layer comprising a second portion of said electrode metal; a second electrode layer formed on said metal oxide.
- 2. A The semiconductor device as recited in claim 1 wherein said electrode metal is tantalum, titanium, cobalt, nickel or molybdenum.
- 3. The semiconductor device as recited in claim 2 wherein said metal silicide is tantalum silicide, titanium silicide, cobalt silicide, nickel silicide or molybdenum silicide.
- 4. The semiconductor device as recited in claim 1 further comprising a transistor electrically connected to said MOM capacitor.
- 5. The semiconductor device as recited in claim 4 wherein said transistor is a CMOS or BiCMOS transistor.
- 6. The semiconductor device as recited in claim 5 comprising a plurality of CMOS or BiCMOS transistor and a plurality of MOM capacitor.
Parent Case Info
This Application is a Divisional of prior application Ser. No. 09/418,106 filed on Oct. 14, 1999, entitled “METHOD OF FORMING METAL OXIDE METAL CAPACITORS USING MULTI-STEP RAPID THERMAL PROCESS AND A DEVICE FORMED THEREBY,” to Siddhartha Bhowrnik, et al., now U.S. Pat. No. 6,323,078. The above-listed Application is commonly assigned with the present invention and is incorporated herein by reference as if reproduced herein in its entirety under Rule 1.53(b).
US Referenced Citations (5)