This invention relates generally to semiconductor fabrication.
As CMOS technology continues to scale further into the sub-micron region, the width of the gate on metal oxide semiconductor (MOS) transistors and the thickness of the gate oxide are constantly being reduced MOS transistors gates are formed using a conductive material such as metals, silicides, and doped polycrystalline silicon (polysilicon). For MOS transistor gates formed using doped polysilicon, metal silicides are often formed on the gate structure to reduce the sheet resistance of the gate and to ensure proper electrical contract.
The self-aligned process used to fabricate MOS transistors and other processes require the formation of a sidewall structure. Along with the reduction in MOS transistor gate width, the scaling of CMOS technology also requires that the width of the sidewall structures be reduced. Gate fabrication techniques utilize an etching process, such as plasma etching or wet chemical etching, to chemically remove material to form the microelectronic devices.
Some etching processes used in fabricating the gate remove material that would otherwise be beneficial to the construction or operation of the microelectronic device. For example,as illustrated in
The recess in the substrate can degrade the performance of the transistor and increase its variability. A thick smile oxide can reduce overlap capacitance and reduce transistor drive current. It is therefore desirable to minimize the silicon recess and “smile oxide” in the fabrication of the transistor structure. This present teachings provide several fabrication techniques to minimize the recess and smile oxide and improve performance.
An embodiment of the present disclosure is directed to a method of fabricating a semiconductor device. The method comprises forming a polysilicon gate on an active region of the semiconductor device. The method also comprises depositing an oxide layer covering the gate, re-oxidizing a portion of the polysilicon of the gate and the silicon substrate to grow a thin silicon oxide layer on the gate and substrate, forming a sidewall layer covering the oxide layer, and removing portions of the sidewall layer and the oxide layer to from spacers on sidewalls of the gate.
Another embodiment of the present disclosure is directed to a method of fabricating a semiconductor device. The method comprises forming a gate on an active region of the semiconductor device. The gate comprises polysilicon. The method also comprises re-oxidizing a portion of the polysilicon of the gate to form a silicon oxide layer on the gate, forming a sidewall layer covering the oxide layer, and removing portions of the sidewall layer and the oxide layer to from spacers on sidewalls of the gate.
Additional embodiments of the disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present disclosure. The embodiments of the disclosure will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments.
According to embodiments of the present disclosure, a method of forming sidewall spacers can reduce formation of recesses in the substrate of a semiconductor device and can minimize the amount of smile of the gate. In the method, silicon of the substrate and polysilicon of the gate is re-oxidized/annealed after formation of the gate. The substrate and gate are re-oxidized by performing an anneal in an inert atmosphere or ambient. The substrate and gate may be re-oxidized/annealed after depositing an oxide layer covering the gate. Additionally, the substrate and gate may be re-oxidized/annealed after forming the gate without depositing the oxide layer.
By re-oxidation/anneal, the method reduces recesses formed in the substrate during fabrication. By decreasing recess in the substrate, the performance of semiconductor device is improved. Further, the re-oxidation/anneal densifies the oxide layer making it resistant to etch processes, drives in dopants trapped near the surface, and reduces thickness variations in the oxide layer.
Reference will now be made in detail to the exemplary embodiments of the present disclosure, an example of which is illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
In the following description, reference is made to the accompanying drawings that form a part thereof, and in which is shown by way of illustration specific exemplary embodiments which may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the invention. The following description is, therefore, merely exemplary.
Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Moreover, all ranges disclosed herein are to be understood to encompass any and all sub-ranges subsumed therein. For example, a range of “less than 10” can include any and all sub-ranges between (and including) the minimum value of zero and the maximum value of 10, that is, any and all sub-ranges having a minimum value of equal to or greater than zero and a maximum value of equal to or less than 10, e.g., 1 to 5.
According to embodiments of the present disclosure, a semiconductor fabrication process may include a method of forming sidewall spacers that reduces formation of recess in the substrate of a semiconductor device.
Method 100 begins with a gate of a semiconductor device being formed on a substrate (stage 102). The substrate may be any type of substrate on which the semiconductor device, such as a MOSFET, may be formed. For example, the substrate may be a silicon wafer, a silicon wafer with previously embedded devices, an epitaxial layer grown on a wafer, a semiconductor on insulation (“SOI”) system, or other suitable substrates having any suitable crystal orientation.
The gate may be formed using any suitable growth and/or deposition techniques available in semiconductor processing and may be formed of any suitable material or combination of materials. For example, the gate may be formed by depositing or growing a gate insulator layer on the substrate and forming a gate material layer or layers on the gate insulator layer. Then, the gate insulator layer and gate material layer may be patterned and portions removed using suitable and well-known techniques, such as etching, polishing, and the like, to form the gate. One skilled in the art will realize that the gate may include additional well-known components.
Next, an ion implantation is performed to create a source region and a drain region on either side of the gate (stage 104). The ion implantation may be performed using any suitable techniques available in semiconductor processing and any suitable dopant to form the source and drain regions.
The ion impanation stage may optionally performed after forming the gate. One skilled in the art will realize that the ion implantation may be performed at any stage during the semiconductor fabrication process.
Then, an oxide layer is formed to cover the gate and portions of the substrate (stage 106). According to embodiments of the present disclosure, the oxide layer is utilized during the re-oxidation/anneal of the gate and substrate. Additionally, the oxide layer is utilized as part of sidewall spacers of the gate. The oxide layer may be formed using any suitable growth and/or deposition techniques available in semiconductor processing and may be formed from any suitable material or combination of materials.
Next, the silicon of the substrate and the polysilicon of the gate can be re-oxidize/anneal to form a re-oxidized layer (stage 108). Re-oxidation/anneal may be achieved using any suitable method to form a re-oxidized layer in the materials of the substrate and gate. For example, an anneal, such as a rapid thermal anneal, spike anneal, ultra-high temperate anneal or combination thereof, may be performed in an inert atmosphere or ambient.
By re-oxidizing/annealing the substrate, method 100 reduces recesses formed in the substrate during fabrication. By preventing recesses in the gate, the performance of the semiconductor device may be increased. Further, the re-oxidation/anneal densities the oxide layer making it resistant to etch processes. Moreover, by re-oxidizing/annealing the substrate, dopants trapped near the surface of the substrate can be driven in rather than lost.
Then, a sidewall layer is formed covering the gate and portions of the substrate (stage 110). The sidewall layer may be formed using any suitable growth and/or deposition techniques available in semiconductor processing and may be formed from any suitable material or combination of materials.
After that, portions of the sidewall layer and the oxide layer are removed (stage 112). The portions are removed in order to from spacers on the sidewall of the gate. Additionally, the portions are removed in order to expose the substrate and the top of the gate. Portions of the sidewall layer and the oxide layer may be removed using any suitable material removal techniques available in semiconductor processing, such as etch processes.
One skilled in the art will realize that additional semiconductor fabrication processes may be performed to complete the semiconductor device. Additionally, one skilled in the art will realize that additional semiconductor device may be fabricated to operate with the semiconductor device fabricated by method 100.
Method 150 begins with a gate of a semiconductor device being formed on a substrate (stage 152). The substrate may be any type of substrate on which the semiconductor device, such as a MOSFET, may be formed. For example, the substrate may be a silicon wafer, a silicon wafer with previously embedded devices, an epitaxial layer grown on a wafer, a SOI system, or other suitable substrates having any suitable crystal orientation.
The gate may be formed using any suitable growth and/or deposition techniques available in semiconductor processing and may be formed of any suitable material or combination of materials. For example, the gate may be formed by depositing or growing a gate insulator layer on the substrate and forming a gate material layer or layers on the gate insulator layer. Then, the gate insulator layer and gate material layer may be patterned and portions removed using suitable and well-known techniques, such as etching, polishing, and the like, to form the gate. One skilled in the art will realize that the gate may include additional well-known components.
Next, an ion implantation is performed to create a source region and a drain region on either side of the gate (stage 154). The ion implantation may be performed using any suitable techniques available in semiconductor processing and any suitable dopant to form the source and drain regions.
The ion impanation stage may optionally performed after forming the gate. One skilled in the art will realize that the ion implantation may be performed at any stage during the semiconductor fabrication process.
Next, the silicon of the substrate and polysilicon of the gate can be re-oxidize/anneal to form a re-oxidized layer in the gate and substrate (stage 156). Re-oxidation may be achieved using any suitable method to form a re-oxidized layer in the materials of the gate and substrate. For example, an anneal may be performed in an inert atmosphere or oxidizing ambient.
By re-oxidizing/annealing the substrate and the gate, method 150 reduces recesses formed in the substrate during fabrication. By preventing recesses in the gate, the performance of the semiconductor device may be increased.
Additionally, during the re-oxidization/anneal, an oxide layer may be formed to cover the gate and portions of the substrate. The oxide layer may be formed from any suitable material or combination of materials depending on the material of the gate and substrate and the anneal performed to re-oxidize the gate and substrate.
Then, a sidewall layer is formed covering the gate and portions of the substrate (stage 158). The sidewall layer may be formed using any suitable growth and/or deposition techniques available in semiconductor processing and may be formed from any suitable material or combination of materials.
After that, portions of the sidewall layer and the oxide layer (if formed) are removed (stage 160). The portions are removed in order to from spacers on the sidewall of the gate. Additionally, the portions are removed in order to expose the substrate and the top of the gate. Portions of the sidewall layer and the oxide layer (if formed) may be removed using any suitable material removal techniques available in semiconductor processing, such as etch processes.
One skilled in the art will realize that additional semiconductor fabrication processes may be performed to complete the semiconductor device. Additionally, one skilled in the art will realize that additional semiconductor device may be fabricated to operate with the semiconductor device fabricated by method 150.
As mentioned above, the method of forming sidewalls spacers may be utilized in forming a semiconductor device such as a MOSFET.
Buried oxide layer 202 may be formed from any suitable oxide material. Likewise, substrate 204 may be formed from any suitable semiconductor material, such as silicon. For example, substrate 204 may be a silicon wafer with an oxide layer 202, such as silicon dioxide (SiO2), buried in the silicon wafer.
Substrate 204 may include an active region formed under gate 206. The active region may be either an N-type active region or a P-type active region depending on the particularly type of MOSFET 200. The well region may be formed using any suitable techniques used in semiconductor processing, such as ion implantation.
Gate 206 may include a gate insulator 208 and gate material 210. Gate 206, including gate insulator 208 and gate material 210, may be formed from any suitable material or combination of materials. For example, gate insulator 208 may be formed of SiO2, nitrided SiO2, Hafnium Oxide (HfO2), Hafnium Silicate (HfSiO4), and the like. For example, gate material 210 may be formed of polysilicon and the like.
Gate 206 may be formed using any suitable growth and/or deposition techniques available in semiconductor processing. For example, gate 206 may be formed by depositing or growing a gate insulator layer on substrate 204 and forming a gate material layer on the gate insulator layer. Then, the gate insulator layer and gate material layer may be patterned and portions removed using suitable and well-known techniques to form a MOSFET gate. One skilled in the art will realize that gate 206 is exemplary and that gate 206 may include additional well-known components.
As illustrated in
Although not illustrated in
As illustrated in
Oxide layer 216 may be formed to any suitable thickness to affect the re-oxidation of gate material 210 and serve as a spacer on gate 206. For example, oxide layer 216 may be formed to a thickness ranging from approximately 20 Å to 70 Å.
As illustrated in
One skilled in the art will realize that this anneal process may be carried out at any suitable temperature for any suitable time period. For example, a spike anneal can be carried out at about 900 degrees C. to about 1000 degrees C., or a flash/laser anneal can be carried out at about 1150 degrees C. to about 1400 degrees C.
Re-oxidized layer 218 may be formed to any suitable thickness. For example, re-oxidized layer 218 may be formed to approximately 5 Å.
By re-oxidizing/annealing the substrate, recesses formed in the substrate during fabrication may be reduced. By preventing recesses in the gate, the performance of the semiconductor device may be increased. Further, the re-oxidation/anneal densifies the oxide layer making it resistant to etch processes. Moreover, by re-oxidizing/annealing the substrate, dopants trapped near the surface of the substrate can be driven in rather than lost.
As illustrated in
Sidewall layer 220 may be formed using any suitable growth and/or deposition techniques available in semiconductor processing. For example, sidewall layer 220 may be formed by chemical vapor deposition (CVD), atmospheric pressure CVD (APCVD), Low Pressure CVD (LPCVD), plasma enhanced CVD (EPCVD), rapid thermal CVD (RTCVD), metal-organic CVD (MOCVD), physical vapor deposition (PVD), and the like.
As illustrated in
In the process described above with reference to
As mentioned above, a substrate may be re-oxidized without first forming a gate oxide layer.
Buried oxide layer 302 may be formed from any suitable oxide material. Likewise, substrate 304 may be formed from any suitable semiconductor material, such as silicon. For example, substrate 304 may be a silicon wafer with an oxide layer 302, such as silicon dioxide (SiO2), buried in the silicon wafer.
Substrate 304 may include an active region formed under gate 306. The active region may be either an N-type active region or a P-type active region depending on the particularly type of MOSFET 300. The well region may be formed using any suitable techniques used in semiconductor processing, such as ion implantation.
Gate 306 may include a gate insulator 308 and gate material 310. Gate 306, including gate insulator 308 and gate material 310, may be formed from any suitable material or combination of materials. For example, gate insulator 308 may be formed of SiO2, nitrided SiO2, HfO2, HfSiO4, and the like. For example, gate material 310 may be formed of polysilicon and the like.
Gate 306 may be formed using any suitable growth and/or deposition techniques available in semiconductor processing. For example, gate 306 may be formed by depositing or growing a gate insulator layer on substrate 304 and forming a gate material layer on the gate insulator layer. Then, the gate insulator layer and gate material layer may be patterned and portions removed using suitable and well-known techniques to form a MOSFET gate. One skilled in the art will realize that gate 306 is exemplary and that gate 306 may include additional well-known components.
As illustrated in
Although not illustrated in
As illustrated in
One skilled in the art will realize that this anneal process may be carried out at any suitable temperature for any suitable time period. For example, a spike anneal can be carried out at about 900 degrees C. to about 1000 degrees C., or a flash/laser anneal can be carried out at about 1150 degrees C. to about 1400 degrees C. Re-oxidized layer 316 may be formed to any suitable thickness.
During the anneal, an oxide layer 318 may be formed on the substrate and portions of gate 306. Oxide layer 318 may be formed to any suitable thickness that may be achieved during the anneal process. For example, oxide layer 318 may be formed to a thickness ranging from approximately 20 Å to 70 Å.
By re-oxidizing/annealing the substrate, recesses formed in the substrate during fabrication may be reduced. By preventing recesses in the gate, the performance of the semiconductor device may be increased. Further, the re-oxidation/anneal densifies the oxide layer making it resistant to etch processes. Moreover, by re-oxidizing/annealing the substrate, dopants trapped near the surface of the substrate can be driven in rather than lost.
As illustrated in
Sidewall layer 320 may be formed using any suitable growth and/or deposition techniques available in semiconductor processing. For example, sidewall layer 320 may be formed by CVD, APCVD, LPCVD, EPCVD, MOCVD, RTCVD, PVD, and the like.
As illustrated in
In the process described above with reference to
Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.