Claims
- 1. A method of forming a doped polysilicon layer in a semiconductor device, comprising the steps of:
- (A) forming a polysilicon layer having grain boundaries on a semiconductor substrate;
- (B) annealing the polysilicon layer in the presence of NH.sub.3, wherein the annealing is conducted under conditions wherein a silicon-nitrogen material is formed at the grain boundaries of the polysilicon layer; and
- (C) doping boron ions into the polysilicon layer by ion implantation, wherein the silicon-nitrogen material formed at the grain boundaries inhibits diffusion of the boron ions along the grain boundaries.
- 2. The method of claim 1, wherein annealing step (B) further comprises the steps of patterning and etching anisotropically the polysilicon layer.
- 3. The method of claim 1, wherein doping step (C) further comprises the step of annealing the polysilicon layer.
- 4. The method of claim 1, wherein the boron ions comprise BF.sub.2 ions.
- 5. The method of claim 1, wherein the nitrogen compound of step (B) comprises NH.sub.3.
- 6. A method of manufacturing a PMOSFET in a semiconductor device, comprising the steps of:
- (A) forming an active region and an insulation region on an n-type semiconductor substrate, and forming a gate insulating layer on the semiconductor substrate;
- (B) depositing a polysilicon layer having grain boundaries on the gate insulating layer, and annealing the polysilicon layer in the presence of NH.sub.3, wherein the annealing is conducted under conditions wherein a silicon-nitrogen material is formed at the grain boundaries of the polysilicon layer;
- (C) forming a gate line by patterning and etching the polysilicon layer; and
- (D) implanting boron ions comprising BF.sub.2 ions into the semiconductor substrate, wherein the silicon-nitrogen material formed at the grain boundaries inhibits diffusion of the boron ions along the grain boundaries.
- 7. The method of claim 6, wherein the implanting step further comprises the step of annealing, wherein impurity ions diffuse into the semiconductor substrate.
- 8. The method of claim 6, wherein the BF.sub.2 ions are implanted into the gate and into the active region to form source and drain regions.
- 9. The method of claim 6, wherein the gate insulating layer comprises silicon oxide.
- 10. A method of manufacturing a PMOSFET in a semiconductor device, comprising the steps of:
- (A) forming an active region and an insulation region on an n-type semiconductor substrate, and growing a gate insulating layer on the semiconductor substrate:
- (B) depositing a polysilicon layer having grain boundaries on the gate insulating layer, and forming a gate line by patterning the polysilicon layer;
- (C) annealing the polysilicon layer in the presence of NH.sub.3, wherein the annealing is conducted under conditions wherein a silicon-nitrogen material is formed at the grain boundaries of the polysilicon layer; and
- (D) implanting boron ions comprising BF.sub.2 ions into a surface of the semiconductor substrate, wherein the silicon-nitrogen material formed at the grain boundaries inhibits diffusion of the boron ions along the grain boundaries.
- 11. The method of claim 10, wherein the implanting step further comprises the step of annealing, wherein the impurity ions diffuse into the semiconductor substrate.
- 12. A method of manufacturing a PMOSFET in a semiconductor device, comprising the steps of:
- (A) forming a gate insulating layer on an n-type semiconductor substrate;
- (B) depositing a polysilicon layer having grain boundaries on the gate insulating layer, and annealing the polysilicon layer in the presence of NH.sub.3, wherein the annealing is conducted under conditions wherein a silicon-nitrogen material is formed at the grain boundaries of the polysilicon layer;
- (C) forming a gate electrode by patterning the polysilicon layer; and
- (D) implanting impurity ions into the semiconductor substrate, wherein the silicon-nitrogen material formed at the grain boundaries inhibits diffusion of the boron ions along the grain boundaries.
- 13. The method of claim 12, wherein the impurity ions comprise BF.sub.2 ions.
- 14. The method of claim 12, wherein the gas containing a nitrogen compound comprises NH.sub.3.
- 15. The method of claim 12, wherein the implanting step further comprises the step of annealing, wherein the impurity ions diffuse into the semiconductor substrate.
- 16. The method of claim 1, wherein annealing step (B) is carried out in a temperature range of about 700.degree. to 1000.degree. C.
- 17. The method of claim 6, wherein the annealing step is carried out in a temperature range of about 700.degree. to 1000.degree. C.
- 18. The method of claim 10, wherein the annealing step is carried out in a temperature range of about 700.degree. to 1000.degree. C.
- 19. The method of claim 12, wherein the annealing step is carried out in a temperature range of about 700.degree. to 1000.degree. C.
Priority Claims (1)
Number |
Date |
Country |
Kind |
93-22628 |
Oct 1993 |
KRX |
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Parent Case Info
This application is a continuation of Ser. No. 08/628,390 filed on Apr. 5, 1996, abandoned, which is a division of Ser. No. 08/330,481, filed Oct. 28, 1994, now abandoned.
US Referenced Citations (4)
Foreign Referenced Citations (1)
Number |
Date |
Country |
59-161837 |
Sep 1984 |
JPX |
Divisions (1)
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Number |
Date |
Country |
Parent |
330481 |
Oct 1994 |
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Continuations (1)
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Number |
Date |
Country |
Parent |
628390 |
Apr 1996 |
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