Method of making an isolation trench and resulting isolation trench

Abstract

A method of forming and resulting isolation region, which allows for densification of an oxide layer in the isolation region. One exemplary embodiment of the method includes the steps of forming a first trench, forming an oxide layer on the bottom and sidewalls of the trench, forming nitride spacers on the lined trench, and thereafter etching the silicon beneath the first trench to form a second trench area. An oxide layer is then deposited to fill the second trench. Densificiation of the isolation region is possible because the silicon is covered with nitride, and therefore will not be oxidized. Light etches are then performed to etch the oxide and nitride spacer area in the first trench region. A conventional oxide fill process can then be implemented to complete the isolation region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts a prior art semiconductor substrate including a high aspect ratio isolation trench.

FIG. 2 is a view of a semiconductor device with a trench formed in a semiconductor substrate at a first stage of processing, in accordance with an exemplary method of the present invention.

FIG. 3 is a view of the FIG. 2 semiconductor device at a processing stage subsequent to FIG. 2, in accordance with an exemplary embodiment of the invention.

FIG. 4 is a view of the FIG. 3 semiconductor device at a processing stage subsequent to FIG. 3, in accordance with the exemplary embodiment of the invention.

FIG. 5 is a view of the FIG. 4 semiconductor device at a processing stage subsequent to FIG. 4, in accordance with the exemplary embodiment of the invention.

FIG. 6 is a view of the FIG. 5 semiconductor device at a processing stage subsequent to FIG. 5, in accordance with the exemplary embodiment of the invention.

FIG. 7 is a view of the FIG. 6 semiconductor device at a processing stage subsequent to FIG. 6, in accordance with the exemplary embodiment of the invention.

FIG. 8 is a view of the FIG. 7 semiconductor device at a processing stage subsequent to FIG. 7, in accordance with the exemplary embodiment of the invention.

FIG. 9 is a view of the FIG. 8 semiconductor device at a processing stage subsequent to FIG. 8, in accordance with the exemplary embodiment of the invention.

FIG. 10 is a view of the structure of a memory array in a conventional NAND type flash memory.

FIG. 11 is a block diagram of a computer system using a memory cell device having trench isolation regions formed by the exemplary method shown in FIGS. 2-9.

Claims

1-29. (canceled)

30. An isolation trench comprising: a first trench area formed in a substrate having sidewalls and a bottom;a second trench area formed at the bottom of the first trench area;a densified oxide layer formed in the second trench area; andan insulating material filling said first trench area.

31. The isolation trench of claim 30, wherein said densified oxide layer is a TEOS layer.

32. The isolation trench of claim 30, wherein said first trench has a first width and said second trench area has a second width, that is less than the first width.

33. The isolation trench of claim 30, wherein said second trench is formed to a depth of about 1000 to about 2000 Angstroms in the substrate.

34. A memory device comprising: at least one isolation region comprising:a first trench area formed in the substrate having sidewalls and a bottom;a second trench area formed at the bottom of the first trench area;a densified oxide layer formed in the second trench; andan insulating material filling said first trench region.

35. The memory device of claim 34, wherein the memory device is a flash memory device comprising a plurality of flash memory elements in an array area and circuitry in a periphery area.

36. The memory device of claim 34, wherein the isolation region is formed between two adjacent flash memory elements.

37. The memory device of claim 34, wherein the isolation region is formed between a flash memory element and said periphery area.

38. The memory device of claim 35, wherein said densified oxide layer is a TEOS layer.

39. The memory device of claim 35, wherein said first trench has a first width and said second trench area has a second width, that is less than said first width.

40. The memory device of claim 35, wherein said at least one isolation comprises: a first isolation trench formed between two adjacent flash memory elements; anda second isolation trench formed between one flash memory element and said periphery area.

41. An isolation trench comprising: a first trench area arranged in a substrate and having sidewalls and a bottom;a second trench area arranged in the substrate at the bottom of the first trench area and having sidewalls and a bottom;a first insulating layer formed along the sidewalls and bottom of the first trench; anda second insulating layer formed along the sidewalls and bottom of the second trench area.

42. The isolation trench of claim 41, wherein the second insulating layer comprises a densified oxide layer and the first insulating layer comprises an oxide layer.

43. The isolation trench of claim 41, wherein the second insulating layer completely fills the second trench.

44. The isolation trench of claim 43, wherein a third insulating layer completely fills an area of the first trench not occupied by the first insulating layer.

45. the isolation trench of claim 44, wherein the isolation trench is arranged next to a second isolation trench having a first trench area arranged in a substrate and having sidewalls and a bottom, a second trench area arranged in the substrate at the bottom of the first trench area and having sidewalls and a bottom, a first insulating layer formed along the sidewalls and bottom of the first trench, and a second insulating layer formed along the sidewalls and bottom of the second trench area, wherein a third insulating layer completely fills an area of the first trench not occupied by the first insulating layer and an area of the second trench not occupied by the second insulating layer.

46. The isolation trench of claim 45, wherein the isolation trench and the second isolation trench are arranged on sides of a flash memory element.

47. The isolation trench of claim 44, wherein the first insulating layer comprises an oxide layer, the second insulating layer comprises a densified oxide layer, and the third insulating layer comprises an oxide layer.

48. The isolation trench of claim 41, wherein a third insulating layer completely fills an area of the first trench not occupied by the first insulating layer and an area of the second trench not occupied by the second insulating layer.

49. The isolation trench of claim 48, wherein the first insulating layer comprises an oxide layer, the second insulating layer comprises a densified oxide layer, and the third insulating layer comprises an oxide layer.