Claims
- 1. A method of manufacturing a bipolar transistor for achieving high-speed operation, said method comprising:
- a first step of oxidizing the surface of a semiconductor substrate for forming a first conductivity type monocrystal silicon layer on the same;
- a second step of forming an isolation region by an insulation film for inter-element isolation on a region of said monocrystal silicon layer other than an element region;
- a third step of introducing first conductivity type impurity into a region of said monocrystal silicon layer close to said isolation film for inter-element isolation and activating said impurity by heat treatment to form a collector electrode extracting layer;
- a fourth step of forming a first insulation layer on said monocrystal silicon layer and said insulation film for inter-element isolation and further depositing a first polycrystal silicon layer introduced with second conductivity type impurity;
- a fifth step of partially opening said first polycrystal silicon layer on said element region and subsequently opening said first insulation layer for partially exposing a surface region of said monocrystal silicon layer other than a part provided with said collector electrode extracting layer;
- a sixth step of depositing a second conductivity type second polycrystal silicon layer on said first polycrystal silicon layer and said exposed region of said monocrystal silicon layer;
- a seventh step of diffusing second conductivity type impurity from said first and second polycrystal silicon layers into said monocrystal silicon layer by heat treatment for forming a second conductivity type monocrystal silicon layer on a surface part of said first conductivity type monocrystal silicon layer;
- an eighth step of partially removing said first and second polycrystal silicon layers and said first and second conductivity type monocrystal silicon layers by anisotropic etching over the entire chip surface to leave a polycrystal silicon layer having a side wall region connected with said second conductivity type monocrystal silicon layer only on said first insulation layer;
- a ninth step of patterning said polycrystal silicon layer formed in said eighth step to serve as an electrode extracting region of said second conductivity type monocrystal silicon layer;
- a tenth step of depositing a nitride film over the entire chip surface and thereafter performing anisotropic etching for forming a side wall of said nitride film only on side walls of said first and second conductivity type monocrystal silicon layers and a part of said polycrystal silicon layer;
- an eleventh step of oxidizing the entire chip surface and thereafter removing said nitride film formed in said tenth step;
- a twelfth step of depositing a second conductivity type third polycrystal silicon layer on the entire chip surface and thereafter diffusing second conductivity type impurity from said third polycrystal silicon layer to said first and second conductivity type monocrystal silicon layers by heat treatment;
- a thirteenth step of coating an insulating material containing high concentration of first conductivity type impurity on the entire chip surface and thereafter diffusing said first conductivity type impurity from said insulating material into said third polycrystal silicon layer and a part of said second conductivity type monocrystal silicon layer by heat treatment;
- a fourteenth step of removing said insulating material and thereafter patterning said third polycrystal silicon layer to serve as an electrode extracting region of said first conductivity type diffusion layer formed in said monocrystal silicon layer in said thirteenth step;
- a fifteenth step of forming contact holes in said insulation layer on said collector electrode extracting layer formed in said third step and in said insulation layer on said polycrystal silicon layer formed in said eighth step respectively; and
- a sixteenth step of forming a collector electrode interconnection layer connected to said collector electrode extracting region through said contact hole, a base electrode interconnection layer connected to said polycrystal silicon layer formed in said eighth step through said contact hole and an emitter electrode interconnection layer directly connected to said third polycrystal silicon layer.
- 2. A method of manufacturing a bipolar transistor in accordance with claim 1, further comprising a step of forming silicide layers on lower parts of said contact holes and a surface part of said third polycrystal silicon layer subsequently to said fifteenth step.
Priority Claims (1)
Number |
Date |
Country |
Kind |
61-287325 |
Dec 1986 |
JPX |
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Parent Case Info
This is a division, of application Ser. No. 07/115,049, filed on 10/30/87, abandoned.
US Referenced Citations (13)
Divisions (1)
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Number |
Date |
Country |
Parent |
115049 |
Oct 1987 |
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