Claims
- 1. A method of manufacturing probe cards for use in testing integrated circuits, said probe card including a plurality of probe wires terminating in respective probe points arranged in a probe point array, said method comprising:
- (a) providing a checkplate having a planar measurement surface with a conductivity transition border formed thereon in which the resistance between the surface of said checkplate and a measurement terminal varies between two values on opposite sides of said border, said checkplate having a known position with respect to said holder;
- (b) sequentially clamping each of said probe wires in a holder;
- (c) scanning said probe point across said border so that said probe point contacts said measurement surface from one side of said conductivity transition border to the other during said scan;
- (d) monitoring the impedance between said probe point and said measurement terminal during said scan in order to detect a change in impedance between said probe point and said measurement terminal when said probe point reaches said conductivity transition border;
- (e) determining the position of said probe card relative to said checkplate when a change in impedance occurs for said probe point checkplate when a change in impedance occurs for said probe point as said probe point reaches said conductivity transition border, thereby determining the position of said probe point relative to said probe card;
- (f) attaching said probe wire to said probe card; and
- (g) repeating steps (b)-(f) until all of said probe wires have been attached to said probe card.
Parent Case Info
This application is a division of U.S. patent application Ser. No. 07/254,269, filed Oct. 5, 1988 now U.S. Pat. No. 4,918,379 issued Apr. 17, 1990.
US Referenced Citations (4)
Divisions (1)
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Number |
Date |
Country |
Parent |
254269 |
Oct 1988 |
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