Claims
- 1. A method of producing a semiconductor device comprising the steps of:
- preparing a stacked structure including a base layer, a patterned lower layer formed on a surface of said base layer, an intermediate layer which covers the surface of said base layer in its entirety including said lower layer, and an upper layer which covers a surface of said intermediate layer in its entirety, said lower layer having an etching rate greater than an etching rate of said intermediate layer;
- patterning said upper and lower layers in a chip region containing electrically coupled elements that form part of an electric circuit on said base layer so that said upper layer and said intermediate layer are aligned to one side surface of said lower layer in at least a part of said chip region; and
- patterning said upper layer in a peripheral region including no elements which form said electric circuit so that said intermediate layer and said upper layer cover one side surface of said lower layer in at least a part of said peripheral region, said peripheral region surrounding said chip region on said base layer.
- 2. The method as claimed in claim 1 wherein said base layer is formed on a substrate, said base layer having an etching rate greater than the etching rate of said intermediate layer.
- 3. The method as claimed in claim 1 wherein said upper layer has an etching rate greater than an etching rate of said lower layer.
- 4. The method as claimed in claim 1 wherein said upper and lower layers are made of a material selected from a group consisting of polysilicon and polycide.
- 5. The method as claimed in claim 1 wherein said base layer is SiO.sub.2.
- 6. The method as claimed in claim 1 wherein said intermediate layer is made of a material selected from a group consisting of SiN and Ta.sub.2 O.sub.3.
- 7. The method as claimed in claim 1 wherein said two patterning steps use an anisotropic dry etching for etching at least said intermediate layer,
- 8. A method of producing a semiconductor device comprising the steps of:
- forming a lower layer on a surface of a base layer;
- patterning said lower layer to expose side surfaces of said lower layer and parts of the surface of said base layer;
- forming an intermediate layer which covers the surface of said base layer in its entirety including said lower layer, said intermediate layer having an etching rate smaller than an etching rate of said lower layer;
- forming an upper layer which covers a surface of said intermediate layer in its entirety; and
- patterning said upper layer so that said upper layer and said intermediate layer are aligned to one side surface of said lower layer in at least a part of a chip region containing electrically coupled elements that form part of an electric circuit on said base layer and said intermediate layer and said upper layer cover one side surface of said lower layer in at least a part of a peripheral region which surrounds said chip region including no elements which form said electric circuit on said base layer.
- 9. The method as claimed in claim 8 wherein said base layer is formed on a substrate, said base layer having an etching rate greater than the etching rate of said intermediate layer.
- 10. The method as claimed in claim 8 wherein said upper layer has an etching rate greater than an etching rate of said lower layer.
- 11. The method as claimed in claim 8 wherein said upper and lower layers are made of a material selected from a group consisting of polysilicon and polycide.
- 12. The method as claimed in claim 8 wherein said base layer is SiO.sub.2.
- 13. The method as claimed in claim 8 wherein said intermediate layer is made of a material selected from a group consisting of SiN and Ta.sub.2 O.sub.3.
- 14. The method as claimed in claim 8 wherein said two patterning steps use an anisotropic dry etching for etching at least said intermediate layer.
- 15. The method as claimed in claim 8 wherein said step of patterning said upper layer intensionally leaves a patterned stacked structure on said base layer in said peripheral region, said intermediate layer and said upper layer of said patterned stacked structure covering at least one side surface of said lower layer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
1-127502 |
May 1989 |
JPX |
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Parent Case Info
This is a divisional, of application Ser. No. 07/932,728 filed Aug. 24, 1992, now U.S. Pat. No. 5,391,902 which is a continuation of application Ser. No. 07/524,767 filed on May 17, 1990, now abandoned.
US Referenced Citations (12)
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Divisions (1)
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Number |
Date |
Country |
Parent |
932728 |
Aug 1992 |
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Continuations (1)
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Number |
Date |
Country |
Parent |
524767 |
May 1990 |
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