Claims
- 1. A method for erase defect management in a memory comprising a plurality of memory arrays divided into individually erasable blocks of memory, said method comprising:
- a) executing an erase operation with a high erase voltage on a block of memory in a memory array;
- b) determining if an error occurred for the erase operation;
- c) determining if the high erase voltage is low;
- d) disabling write operations to the memory array, if the high erase voltage is low; and
- e) executing read operations to the memory array, if requested.
- 2. The method of claim 1 wherein the memory comprises flash electrically erasable programmable read only memory (EEPROM) memory cells.
- 3. The method of claim 1 wherein executing an erase operation further comprises:
- i) writing logical ones to the block.
- 4. The method of claim 1 wherein determining if an error occurred further comprises:
- i) comparing data stored in the block with logical ones.
- 5. The method of claim 4 wherein comparing data stored in the block with logical ones further comprises reading data stored in the block.
- 6. The method of claim 1 further comprising:
- f) marking a sector of the block being erased bad, if an erase error occurred and the high erase voltage is not low.
CROSS REFERENCE TO RELATED APPLICATIONS
The present application is a divisional of application Ser. No. 08/511,990 filed Aug. 7,1995 (now U.S. Pat. No. 5,557,194), which is a continuation of application Ser. No. 07/969,749 filed Oct. 30,1992 (now U.S. Pat. No. 5,473,753).
US Referenced Citations (24)
Foreign Referenced Citations (1)
Number |
Date |
Country |
2088442 |
Jul 1993 |
CAX |
Divisions (1)
|
Number |
Date |
Country |
Parent |
511990 |
Aug 1995 |
|
Continuations (1)
|
Number |
Date |
Country |
Parent |
969749 |
Oct 1992 |
|