Claims
- 1. A method of manufacturing a DRAM including a memory cell having one MOS transistor and one stacked capacitor and a peripheral circuit including a MOS transistor, comprising the steps of:
- forming MOS transistors in a memory cell region and in a peripheral circuit region on a main surface of a semiconductor substrate;
- forming a first conductive layer on the entire surface of said semiconductor substrate and patterning the same to form an electrode layer connected to one of impurity regions of the MOS transistor in said memory cell and to form a first interconnection layer connected to one of impurity regions of the MOS transistor in said peripheral circuit extending at least above a gate electrode;
- covering surfaces of said electrode layer and said first interconnection layer with an insulating layer; and
- forming a second conductive layer on the entire surface of said semiconductor substrate and patterning the same to form a lower electrode of said capacitor connected to the other one of the impurity regions of the MOS transistor in said memory cell, and to form a second interconnection layer connected to the other one of the impurity region of the MOS transistor of said peripheral circuit extending at least above said gate electrode.
Priority Claims (1)
Number |
Date |
Country |
Kind |
2-115642 |
May 1990 |
JPX |
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Parent Case Info
This application is a division of application Ser. No. 08/232,315 filed Apr. 25, 1994, U.S. Pat. No. 5,486,712, which is a continuation of Ser. No. 07/690,843 filed Apr. 24, 1991, abandoned.
US Referenced Citations (5)
Foreign Referenced Citations (6)
Number |
Date |
Country |
0161850 |
Nov 1985 |
EPX |
3910033A1 |
Oct 1989 |
DEX |
4113233A1 |
Oct 1991 |
DEX |
4113733A1 |
Oct 1991 |
DEX |
64-80066 |
Mar 1989 |
JPX |
2-76257 |
Mar 1990 |
JPX |
Non-Patent Literature Citations (2)
Entry |
Kaga et al., "A Crown Type Stacked Capacitor Cell for a 1.5V Operation 64 DRAM", Proceedings of 37th Applied Physics Association Conference, 2nd vol., p. 582, 1990. |
Wakamiya et al., "Novel Stacked Capacitor Cell for 64 Mb DRAM", 1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70. |
Divisions (1)
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Number |
Date |
Country |
Parent |
232315 |
Apr 1991 |
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Continuations (1)
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Number |
Date |
Country |
Parent |
690843 |
Apr 1991 |
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