Method of manufacturing a semiconductor device

Abstract

A semiconductor device manufacturing method is disclosed wherein a semiconductor integrated circuit is formed in each of plural semiconductor chip regions of a semiconductor wafer which regions are to become semiconductor chips later and then the semiconductor wafer is cut along scribing regions each provided between adjacent semiconductor chip regions. The semiconductor chip regions are each in a rectangular shape having long sides and short sides. The scribing regions include a first scribing region in contact with the short sides and a second scribing region in contact with the long sides. The width of the second scribing region is smaller than the width of the first scribing region. In a photolithography process, first and second alignment patterns for making alignment in both X and Y directions are all formed in the first scribing region and not formed in the second scribing region. Both improvement of the alignment accuracy and reduction of the semiconductor device manufacturing cost can be attained.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a manufacturing process flow chart showing a semiconductor device manufacturing process according to a first embodiment of the present invention;

FIG. 2 is a conceptual plan view of a semiconductor wafer in the semiconductor device manufacturing process according to the first embodiment;

FIG. 3 is a plan view of a principal portion of the semiconductor wafer in the semiconductor device manufacturing process according to the first embodiment;

FIG. 4 is a plan view of a principal portion of the semiconductor wafer, showing an alignment pattern-formed area and the vicinity thereof on a larger scale;

FIG. 5 is a sectional view of a principal portion in the semiconductor device manufacturing process according to the first embodiment;

FIG. 6 is a sectional view of the principal portion in the semiconductor device manufacturing process which follows FIG. 5;

FIG. 7 is a plan view showing an area which is exposed by one shot in an exposure step in a photolithography process;

FIG. 8 is a plan view of a principal portion of a semiconductor wafer in a semiconductor device manufacturing process as a comparative example;

FIG. 9 is a plan view of a principal portion of the semiconductor wafer in the comparative semiconductor device manufacturing process;

FIG. 10 is a manufacturing process flow chart showing a dicing process for a semiconductor wafer;

FIG. 11 is an explanatory diagram of the wafer dicing process;

FIG. 12 is an explanatory diagram of the wafer dicing process;

FIG. 13 is an explanatory diagram of the wafer dicing process;

FIG. 14 is an explanatory diagram of the wafer dicing process;

FIG. 15 is an explanatory diagram of the water dicing process;

FIG. 16 is a plan view showing a mounted state of a semiconductor chip to an LCD panel;

FIG. 17 is a sectional view of a principal portion, showing a mounted state of the semiconductor chip to the LCD panel;

FIG. 18 is a plan view of a principal portion of a semiconductor wafer in a semiconductor device manufacturing process according to another embodiment of the present invention;

FIG. 19 is a plan view of a principal portion of the semiconductor wafer, showing an alignment pattern-formed area and the vicinity thereof on a larger scale;

FIG. 20 is a plan view of a principal portion of a semiconductor wafer in a semiconductor device manufacturing process according to a further embodiment of the present invention; and

FIG. 21 is a plan view of a principal portion of another semiconductor wafer in the semiconductor device manufacturing process according to the further embodiment.

Claims

1. A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a semiconductor wafer;(b) forming a semiconductor integrated circuit in each of plural semiconductor chip regions of the semiconductor wafer which regions are to become semiconductor chips later; and(c) cutting the semiconductor wafer along a scribing region formed between the plural semiconductor chip regions,wherein the scribing region comprise a first scribing region extending in a first direction and a second scribing region extending in a second direction intersecting the first direction,wherein the width of the second scribing region is smaller than the width of the first scribing region, andwherein two types of alignment patterns for use in a photolithography process are formed in the first scribing region, while no alignment pattern is formed in the second scribing region.

2. The method of claim 1, wherein the two types of alignment patterns are alignment patterns to be used for alignment in directions different from each other.

3. The method of claim 3, wherein the two types of alignment patterns are a first alignment pattern to be used for alignment in the first direction and a second alignment pattern to be used for alignment in the second direction.

4. The method of claim 3, wherein the first alignment pattern comprises patterns arranged repeatedly in the first direction in the first scribing region, andwherein the second alignment pattern comprises patterns arranged repeatedly in the second direction in the first scribing region.

5. The method of claim 3, wherein one of the first and second alignment patterns is a 90° rotated pattern with respect to the other.

6. The method of claim 3, wherein the size in the first direction of the first alignment pattern and the size in the second direction of the second alignment pattern are the same.

7. The method of claim 3, wherein the size in the second direction of the second alignment pattern is smaller than the size in the first direction of the first alignment pattern.

8. The method of claim 3, wherein the width of the second scribing region is not larger than the size in the first direction of the second alignment pattern.

9. The method of claim 1, wherein the first and the second direction are orthogonal to each other.

10. The method of claim 1, wherein the semiconductor chip regions each have a rectangular plane shape having long sides and short sides shorter than the long sides,wherein the first scribing region is in contact with the short sides of the semiconductor chip regions, andwherein the second scribing region is in contact with the long sides of the semiconductor chip regions.

11. The method of claim 10, wherein the semiconductor chips are semiconductor chips for LCD driver.

12. The method of claim 1, wherein the semiconductor chip regions each have a rectangular plane shape having long sides and short sides shorter than the long sides,wherein the first direction is parallel to the short sides of the semiconductor chip regions, andwherein the second direction is parallel to the long sides of the semiconductor chip regions.

13. The method of claim 1, wherein, in the step (b), a TEG pattern is formed in the first scribing region and not formed in the second scribing region.

14. The method of claim 1, wherein, in the step (b), all of the patterns to be formed in the scribing region are formed in the first scribing region and not formed in the second scribing region.

15. The method of claim 1, wherein the two types of alignment patterns are formed for each area exposed by one shot in an exposure step in a photolithography process.

16. The method of claim 1, wherein the step (c) comprises the steps of: (c1) forming a groove in the semiconductor wafer along the first scribing region with use of a first blade;(c2) after the step (c1), cutting the semiconductor wafer at the bottom of the groove along the first scribing region with use of a second blade having a cutting edge thinner than that of the first blade; and(c3) cutting the semiconductor wafer along the second scribing region.

17. The method of claim 16, wherein the semiconductor wafer is cut along the first scribing region in two steps of the steps (c1) and (c2) and is cut along the second scribing region in one step of the step (c3).

18. The method of claim 16, wherein, in the step (c3), the semiconductor wafer is cut along the second scribing region with use of the second blade.

19. The method of claim 16, wherein, in the step (c1), the semiconductor wafer is half-cut, while in the steps (c2) and (c3) the semiconductor wafer is full-cut.

20. The method of claim 16, wherein the two types of alignment patterns formed in the first scribing region in the step (b) are removed in the step (c1).