Claims
- 1. A method of manufacturing an MIS device, comprising the steps of:
- forming a first insulating film on a semiconductor substrate;
- forming a first conductive layer on said first insulating film;
- coating resist on said first conductive layer and selectively removing said resist to form a mask pattern;
- patterning said first conductive layer and said first insulating film by using said mask pattern;
- implanting impurity for forming impurity regions of a relatively low concentration in said semiconductor substrate by using said patterned portions as masks;
- forming a nitride film on surfaces of said insulating film including surfaces of said first conductive layer;
- anisotropically etching said nitride film, leaving said nitride film only on sidewalls of said first conductive layer;
- applying a thermal oxidation process by using said nitride film and said first conductive layer as masks, and forming a second insulating film having a thickness larger than that of said first insulating film on a surface of said semiconductor substrate not covered with said first conductive layer;
- removing said nitride film and forming a second conductive layer on surfaces of said second insulating film including surfaces of said first conductive layer,
- etching said second conductive layer, leaving said second conductive layer only on the sidewalls of said first conductive layer; and
- implanting impurity for forming impurity regions of a relatively high concentration in said semiconductor substrate by using said first and second conductive layers as masks.
- 2. A manufacturing method in accordance with claim 1 further comprising the step of forming a third insulating film on said first conductive layer after the steps of forming said first insulating film and said first conductive layer on said semiconductor substrate.
- 3. A manufacturing method in accordance with claim 1, wherein said second conductive layer is left only on the sidewalls of said first conductive layer by anisotropic etching.
- 4. A manufacturing method in accordance with claim 1, further comprising the step of forming an oxide film on a surface of said first conductive layer, an end of etching of said second conductive layer being detected by using said oxide film.
Priority Claims (4)
Number |
Date |
Country |
Kind |
63-217623 |
Aug 1988 |
JPX |
|
63-233218 |
Sep 1988 |
JPX |
|
63-251113 |
Oct 1988 |
JPX |
|
63-308072 |
Dec 1988 |
JPX |
|
Parent Case Info
This application is a division of application Ser. No. 07/399,947 filed Aug. 31, 1989, now U.S. Pat. No. 5,146,291.
US Referenced Citations (7)
Foreign Referenced Citations (18)
Number |
Date |
Country |
55-53461 |
Apr 1980 |
JPX |
60-229374 |
Nov 1985 |
JPX |
60-235471 |
Nov 1985 |
JPX |
60-261171 |
Dec 1985 |
JPX |
61-36975 |
Feb 1986 |
JPX |
61-119078 |
Jun 1986 |
JPX |
61-201471 |
Sep 1986 |
JPX |
61-201472 |
Sep 1986 |
JPX |
61-201475 |
Sep 1986 |
JPX |
61-258475 |
Nov 1986 |
JPX |
62-49665 |
Mar 1987 |
JPX |
62-160770 |
Jul 1987 |
JPX |
63-44770 |
Feb 1988 |
JPX |
61-201473 |
Apr 1988 |
JPX |
63-168050 |
Jul 1988 |
JPX |
64-764 |
Jan 1989 |
JPX |
2-137335 |
May 1990 |
JPX |
3-127837 |
May 1991 |
JPX |
Non-Patent Literature Citations (2)
Entry |
Paul J. Tsang et al. "Fabrication of High-Performance LDDFET's Oxide Sidewall Sidewall-Spacer Technology," IEEE Transactions on Electron Devices, vol. EL-29, No. 4, Apr. 1982, pp. 590-596. |
Ryuichi Izawa et al. "The Impact of Gate-Drain Overlapped LDD (Gold) for Deep Submicron VLSI's", IEEE Central Research Laboratory, Hitachi Ltd., Kokubunju, Tokyo 1895, Japan, 1987, pp. 38-41. |
Divisions (1)
|
Number |
Date |
Country |
Parent |
399947 |
Aug 1989 |
|