Claims
- 1. A method of making a semiconductor device comprising:
- depositing first and second semiconductor layers of opposite conductivity types on a semiconductor substrate;
- exposing the second semiconductor layer to a flux of ions to produce an electrically isolating region in and penetrating through the first and second semiconductor layers and into the semiconductor substrate;
- etching a via hole penetrating through the first and second semiconductor layers within the electrically isolating region, thereby exposing a side wall of the first and second semiconductor layers within the electrically isolating region; and
- depositing an electrically conducting material in the via hole in contact with the side wall of the first and second semiconductor layers at the electrically isolating region, thereby completing a via hole structure in which the first and second semiconductor films are not electrically connected through the electrically conducting material.
- 2. The method of claim 1 including depositing source, gate, and drain electrodes on the second semiconductor layer to form a field effect transistor and depositing the electrically conducting material in electrical contact with one of the source and gate electrodes.
- 3. The method of claim 1 wherein the substrate is semi-insulating including depositing a plated heat sink on the surface of the substrate opposite the first semiconductor layer.
- 4. The method of claim 3 including depositing the electrically conducting material in electrical contact with the plated heat sink.
- 5. The method of claim 1 wherein the semiconductor substrate is chosen from the group consisting of gallium arsenide and indium phosphide.
- 6. The method of claim 1 wherein the semiconductor substrate is silicon.
- 7. The method of claim 1 including etching the via hole through the substrate, the first semiconductor layer, and finally through the second semiconductor layer.
- 8. The method of claim 7 including depositing the electrically conducting material in the via hole and on the surface of the substrate opposite the first semiconductor layer.
- 9. A method of making a semiconductor device comprising:
- depositing first and second semiconductor layers of opposite conductivity types on a semiconductor substrate;
- etching a via hole penetrating through the first and second semiconductor layers and into the semiconductor substrate, thereby exposing a side wall of the first and second semiconductor layers;
- exposing the surface of the second semiconductor layer to a flux of ions to produce an electrically isolating region in and penetrating through the first and second semiconductor layers and into the semiconductor substrate surrounding the via hole to produce an electrically isolating region adjacent the side wall; and
- depositing an electrically conducting material in the via hole in contact with the side wall of the first and second semiconductor layers at the electrically isolating region, thereby completing a via hole structure in which the first and second semiconductor films are not electrically connected through the electrically conducting material.
- 10. The method of claim 9 including depositing source, gate, and drain electrodes on the second semiconductor layer to form a field effect transistor and depositing the electrically conducting material in electrical contact with one of the source and gate electrodes.
- 11. The method of claim 9 wherein the substrate is semi-insulating including depositing a plated heat sink on the substrate on the surface opposite the first semiconductor layer.
- 12. The method of claim 11 including depositing the electrically conducting material in electrical contact with the plated heat sink.
- 13. The method of claim 9 wherein the semiconductor substrate is chosen from the group consisting of gallium arsenide and indium phosphide.
- 14. The method of claim 9 wherein the semiconductor substrate is silicon.
- 15. The method of claim 9 including etching the via hole through the substrate, the first semiconductor layer, and finally through the second semiconductor layer.
- 16. The method of claim 15 including depositing the electrically conducting material in the via hole and on the surface of the substrate opposite the first semiconductor layer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
2-148181 |
Jun 1990 |
JPX |
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Parent Case Info
This application is a continuation of application Ser. No. 07/700,436, now U.S. Pat. No. 5,225,707 filed May 15, 1991.
US Referenced Citations (13)
Foreign Referenced Citations (3)
Number |
Date |
Country |
0376723 |
Jul 1990 |
EPX |
1-37835 |
Feb 1989 |
JPX |
64-80059 |
Mar 1989 |
JPX |
Non-Patent Literature Citations (2)
Entry |
Sumitani et al., "A High Power Aspect Ratio Via Hole Dry Etching Technique for High Power GaAs MESFET", IEEE GaAs IC Symposium, Oct. 1989, pp. 207-210. |
Kobiki et al., "A Ka-Band GaAs Power MMIC", IEEE Monolithic Circuits Symposium, 1985, pp. 31-34. |
Divisions (1)
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Number |
Date |
Country |
Parent |
700436 |
May 1991 |
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