CROSS-REFERENCE TO RELATED APPLICATION
Priority to Korean patent application number 10-2009-0134122 filed Dec. 30, 2009, the entire disclosure of which is incorporated by reference herein, is claimed.
BACKGROUND
Exemplary embodiments relate generally to a method of manufacturing nonvolatile memory devices and, more particularly, to a method of manufacturing nonvolatile memory devices that is capable of preventing the generation of voids when forming a control gate.
A nonvolatile memory device includes a floating gate for storing data and a control gate for transferring driving voltages.
A method of forming the nonvolatile memory device is described below.
A gate insulating layer and a conductive layer for floating gates are formed over a semiconductor substrate. The conductive layer and the gate insulating layer are patterned to expose the semiconductor substrate, and some of the exposed semiconductor substrate is etched to form trenches for isolation. The trenches are filled with an insulating material to form isolation layers, and an etch process for lowering the height of the isolation layers is performed. A dielectric layer is formed on the entire surface, and a conductive layer for control gates is formed over the dielectric layer.
Meanwhile, with increases in the degree of integration of nonvolatile memory devices, not only the width of the floating gate, but also a gap between neighboring floating gates is narrowed.
Accordingly, after forming the dielectric layer, when forming the conductive layer for control gates, voids can be generated between the conductive layers for floating gates. Thus, voids can be generated on a surface of the dielectric layer and in the control gates.
If voids are generated as described above, resistance of the control gate can be increased when the memory device is operated, and there may be a difference in the electrical characteristics between a region in which voids have occurred and a region in which voids have not occurred. Accordingly, reliability of the nonvolatile memory device may be degraded.
BRIEF SUMMARY
Exemplary embodiments relate to a method of manufacturing nonvolatile memory devices that is capable of preventing the generation of voids in a process of forming a control gate.
A method of manufacturing nonvolatile memory devices according to an aspect of the disclosure comprises forming a plurality of floating gates spaced apart from each other over a semiconductor substrate, forming a dielectric layer on the surface of the floating gates, forming a capping layer on the surface of the dielectric layer, adding impurities to the capping layer, preferably by supplying an impurity source gas to a chamber so that impurities are contained in the capping layer, and forming a control gate over the capping layer containing the impurities.
The capping layer preferably comprises a polysilicon layer.
The impurities contained in the capping layer preferably include at least one of phosphorous (P), nitrogen (N), and oxygen (O).
In one embodiment, PH3 gas is supplied to a chamber in which the semiconductor substrate is loaded so that the phosphorous (P) is contained in the capping layer.
In another embodiment, NH3 gas is supplied to a chamber in which the semiconductor substrate is loaded so that nitrogen (N) is contained in the capping layer.
In yet another embodiment, O2 gas is supplied to a chamber in which the semiconductor substrate is loaded so that oxygen (O) is contained in the capping layer.
Preferably, the PH3 gas, NH3 gas, or O2 gas used in the embodiments exemplified above has a concentration of 5×1019 ion/cm3 to 1×1022 ion/cm3 in the chamber.
Forming the capping layer, supplying the impurity source gas, and forming the control gate preferably are performed in-situ in the same chamber.
The capping layer preferably is formed to a thickness of 5 Å to 50 Å.
The floating gates preferably are formed by stacking an undoped polysilicon layer and a doped polysilicon layer. Preferebly, the doped polysilicon layer is narrower than the undoped polysilicon layer.
Each of the floating gates preferably is narrower in an upper side than in a lower side.
The dielectric layer preferably is formed by stacking an oxide layer, a nitride layer, and an oxide layer or by depositing a high-K layer.
A method of manufacturing nonvolatile memory devices according to another aspect of the disclosure comprises forming a plurality of floating gates spaced apart from each otherover a semiconductor substrate, forming a dielectric layer on an overall structure including the floating gates, forming a first polysilicon layer on the surface of the dielectric layer to prohibit generation of voids on the surface of the dielectric layer, adding phosphorous (P), nitrogen (N), or oxygen (O) impurities to the polysilicon layer by supplying at least one of PH3 gas, NH3 gas, and O2 gas to a chamber in which the semiconductor substrate is loaded, and forming a second polysilicon layer over the first polysilicon layer to fill spaces between the floating gates.
The PH3 gas, NH3 gas, or O2 gas preferably has a concentration of 5×1019 ion/cm3 to 1×1022 ion/cm3 in the chamber.
Forming the first polysilicon layer, containing the impurities in the first polysilicon layer, and forming the second polysilicon layer preferably are performed in-situ in the same chamber.
The first polysilicon layer preferably is formed to a thickness of 5 Å to 50 Å.
The dielectric layer preferably is formed by stacking an oxide layer, a nitride layer, and an oxide layer or by depositing a high-K layer.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A to 1F are cross-sectional views illustrating a method of manufacturing nonvolatile memory devices according to an exemplary embodiment of this disclosure; and
FIGS. 2A to 2H are cross-sectional views illustrating a method of manufacturing nonvolatile memory devices according to another exemplary embodiment of this disclosure.
DESCRIPTION OF EMBODIMENTS
Hereinafter exemplary embodiments of the disclosure are described in detail with reference to the accompanying drawings. The drawing figures are provided to allow those having ordinary skill in the art to understand the scope of the embodiments of this disclosure.
FIGS. 1A to 1F are cross-sectional views illustrating a method of manufacturing nonvolatile memory devices according to an exemplary embodiment of this disclosure.
Referring to FIG. 1A, a gate insulating layer 102, a first conductive layer 104u for a floating gate 104, a second conductive layer 104d, and isolation mask patterns 106 are formed over a semiconductor substrate 100. The gate insulating layer 102 preferably comprises an oxide layer. The first conductive layer 104u preferably comprises an undoped polysilicon layer, and the second conductive layer 104d preferably comprises a doped polysilicon layer. The isolation mask patterns 106 preferably comprise a nitride layer.
Referring to FIG. 1B, the second and first conductive layers (104d and 104u, respectively, of FIG. 1A) and the gate insulating layer (102 of FIG. 1A) are patterned by performing an etch process along the isolation mask patterns 106. Some of the exposed semiconductor substrate 100 is etched to form trenches TC for isolation. Consequently, the gate insulating patterns 102a, the floating gates 104a, and the isolation mask patterns 106 remain over the active regions of the semiconductor substrate 100, and the trenches TC are formed in the isolation regions of the semiconductor substrate 100.
Referring to FIG. 10, the inside of the trenches TC is filled with an insulating material, thereby forming isolation layers 108. More particularly, to fill the inside of the trenches TC, the insulating material is formed to fully cover the top surface of the isolation mask patterns 106. Next, a polishing process (for example, chemical mechanical polishing (CMP)) is performed until the isolation mask patterns 106 are exposed, thereby isolating the insulating materials filled in the inside of the trenches TC and forming the isolation layers 108. The isolation mask patterns 106 are removed, and the height of the isolation layers 108 is lowered to control the effective field height (EFH). Here, the gate insulating patterns 102a preferably are not exposed.
Referring to FIG. 1D, a dielectric layer 110 is formed on the isolation layers 108 and an exposed surface of the floating gates 104a. The dielectric layer 110 preferably is formed by stacking an oxide layer, a nitride layer, and an oxide layer or by depositing a high-K layer.
Referring to FIG. 1E, a capping layer 112 for easily forming a control gate is formed on a surface of the dielectric layer 110.
More particularly, the capping layer 112 preferably comprises a polysilicon layer and preferably is relatively thin (for example 5 Å to 50 Å) by taking the aspect ratio between the floating gates 104a into consideration.
After forming the capping layer 112, impurities are added to the capping layer 112 for the purpose of prohibiting the generation of voids in a subsequent process of forming a third conductive layer (114 of FIG. 1F) for a control gate. More particularly, the impurities added to the capping layer 112 preferably include at least one of phosphorous (P), nitrogen (N), and oxygen (O). To add the impurities to the capping layer 112, an impurity source gas preferably is supplied to a chamber in which the semiconductor substrate 100 is loaded. More particularly, to add phosphorous (P) in the capping layer 112, PH3 gas (i.e., an impurity source gas of a high concentration) preferably is supplied to the chamber. To add nitrogen (N) to the capping layer 112, NH3 gas (i.e., the impurity source gas) preferably is supplied to the chamber. To add oxygen (O) to the capping layer 112, O2 gas (i.e., the impurity source gas) preferably is supplied to the chamber. Thus, at least one of the PH3 gas, the NH3 gas, and the O2 gas preferably is supplied to the chamber so that the impurities are included in the capping layer 112. The gas supplied to the chamber preferably has a concentration in the chamber of 5×1019 ion/cm3 to 1×1022 ion/cm3. If at least one of the PH3 gas, the NH3 gas, and the O2 gas of a high concentration is supplied to the chamber, different impurities are included in the capping layer 112 according to the type of the supplied impurity source gas. The capping layer 112 containing the impurities serves as a seed layer when subsequently forming the third conductive layer 114 for a control gate.
The process of adding the impurities in the capping layer 112 preferably is performed in-situ in the same chamber after forming the capping layer 112.
Referring to FIG. 1F, the third conductive layer 114 for a control gate is formed over the capping layer 112 containing the impurities. The third conductive layer 114 preferably comprises a doped polysilicon layer. In particular, if the third conductive layer 114 is formed over the capping layer 112 including the impurities and the seed layer, the impurities and the seed layer serve as an uniform seed of the third conductive layer 114, and a third conductive layer 114 having grains of an uniform size can be formed. Furthermore, the process of forming the third conductive layer 114 preferably is performed in-situ by using the same chamber after the process of adding the impurities to the capping layer 112 is performed. As described above, since the process of forming the capping layer 112, the process of including the impurities, and the process of forming the third conductive layer 114 can be performed in-situ in the same chamber, the turnaround time can be reduced.
Furthermore, since the capping layer 112 containing the impurities is formed, voids can be prevented from occurring on the surface of the dielectric layer 110 or within the third conductive layer 114 in the process of forming the third conductive layer 114. Since the generation of voids is prevented, an increase of resistance of the control gate can be prevented, thereby improving reliability of the nonvolatile memory devices.
FIGS. 2A to 2H are cross-sectional views illustrating a method of manufacturing nonvolatile memory devices according to another exemplary embodiment of this disclosure.
Referring to FIG. 2A, a gate insulating layer 202, a first conductive layer 204 for floating gates, and isolation mask patterns 206 are formed over a semiconductor substrate 200. The gate insulating layer 202 preferably comprises an oxide layer. The first conductive layer 204 preferably comprises an undoped polysilicon layer, and the isolation mask patterns 206 preferably comprise a nitride layer. Here, the first conductive layer 204 preferably is relatively thin to lower the aspect ratio of trenches (TC of FIG. 2B) in a subsequent process of forming isolation layers (208 of FIG. 2C).
Referring to FIG. 2B, the first conductive layer (204 of FIG. 2A) and the gate insulating layer (202 of FIG. 2A) are patterned by performing an etch process using the isolation mask patterns 206, thereby forming first conductive patterns 204a and gate insulating patterns 202a. Trenches TC are formed by etching some of the exposed semiconductor substrate 200. Here, the trenches TC may have a different aspect ratio depending on the thickness of the first conductive patterns 204a. Thus, if the first conductive patterns 204a are relatively thin, the trenches TC may have a lower aspect ratio, and the generation of voids can be prevented in a gap-fill process of filling the inside of the trenches TC with an insulating material.
Referring to FIG. 2C, the isolation layers 208 are formed within the trenches TC. More particularly, the isolation layers 208 are comprise an insulating material, but may be formed by stacking a fluid insulating layer and a high-density insulating layer to improve the gap-fill characteristic. For example, the bottom of the trenches TC may be filled with a spin on dielectric (SOD) layer (i.e., a fluid insulating material). A thermal treatment process for solidifying the SOD layer is performed because the SOD layer is a fluid material. If the thermal treatment process is performed, the fineness of the SOD layer may be reduced. Accordingly, it is preferred that a high density plasma (HDP) layer (i.e., a high-density insulating layer) be formed over the SOD layer.
Next, the insulating materials are isolated from each other by performing a polishing process (for example, chemical mechanical polishing (CMP)) until the isolation mask patterns (206 of FIG. 2B) are exposed, thereby forming the isolation layers 208. After removing the isolation mask patterns 206, the height of the isolation layers 208 is lowered by performing an etch process to control the effective field height (EFH). Here, the gate insulating patterns 202a are not exposed.
Referring to FIG. 2D, a second conductive layer 210 for floating gates is formed over the isolation layers 208 and the first conductive patterns 204a. The second conductive layer 210 preferably comprises a doped polysilicon layer. The second conductive layer 210 preferably is thicker than first conductive patterns 204a to increase the area of the floating gates. Hard mask patterns 212 for patterning second conductive layer 210 are formed over the second conductive layer 210. The hard mask pattern 212 preferably is narrower than the first conductive pattern 204a.
Referring to FIG. 2E, the second conductive layer 210 is patterned by performing an etch process using the hard mask patterns 212. Thus, second conductive patterns 210a, each being narrower than the first conductive pattern 204a, can be formed over the first conductive patterns 204a for the purpose of lowering the aspect ratio by widening a gap between the second conductive patterns 210a for floating gates upwardly protruding from the isolation layers 208. Thus, in a subsequent process of forming a control gate, voids can be prohibited from occurring in the control gate.
Referring to FIG. 2F, a dielectric layer 214 is formed on a surface of the isolation layers 208 and the first and second conductive patterns 204a and 210a, respectively. The dielectric layer 214 preferably is formed by stacking an oxide layer, a nitride layer, and an oxide layer or by depositing a high-k layer.
Referring to FIG. 2G, a capping layer 216 for easily forming the control gate is formed on a surface of the dielectric layer 214. More particularly, the capping layer 216 preferably comprises a polysilicon layer. The capping layer 216 preferably is formed relatively thin (for example, 5 Å to 50 Å) by taking the aspect ratio between the second conductive patterns 210a into consideration.
After forming the capping layer 216, impurities are added to the capping layer 216 to prevent voids from occurring on the surface of the dielectric layer 214 or within the control gate in a subsequent process of forming a third conductive layer (218 of FIG. 2H) for the control gate. More particularly, the impurities added to the capping layer 216 preferably are at least one of phosphorous (P), nitrogen (N), and oxygen (O). To add the impurities to the capping layer 216, at least one of PH3 gas, NH3 gas, and O2 gas (i.e., an impurity source gas of a high concentration) preferably is supplied to a chamber in which the semiconductor substrate 200 is loaded. If at least one of the PH3 gas, the NH3 gas, and the O2 gas is supplied to the chamber, different impurities are contained in the capping layer 216 depending on the type of the supplied impurity source gas. The capping layer 216 containing the impurities serves as a seed layer when forming the control gate.
The process of containing the impurities in the capping layer 216 preferably is performed in-situ in the same chamber after forming the capping layer 216.
Referring to FIG. 2H, the third conductive layer 218 for the control gate is formed over the capping layer 216. The third conductive layer 218 preferably comprises a doped polysilicon layer. In particular, if the third conductive layer 218 is formed over the capping layer 216 containing the impurities, the capping layer 216 containing the impurities serves as the seed layer, and so the third conductive layer 218 having grains of an uniform size can be formed.
Furthermore, the process of forming the third conductive layer 218 preferably is performed in-situ by using the same chamber after the process of adding the impurities to the capping layer 216 is performed.
Since the process of forming the capping layer 216, the process of containing the impurities, and the process of forming the third conductive layer 218 preferably are performed in-situ in the same chamber as described above, the turnaround time may be reduced.
In the process of forming the third conductive layer 218 as described above, voids can be prevented from occurring in the region between the protruded second conductive patterns 210a for floating gates. Since the generation of voids can be prevented, an increase of resistance of the control gate can be prevented, thereby improving reliability of the nonvolatile memory devices.
According to the disclosure, the capping layer is formed on a surface of the dielectric layer, and impurities for accelerating the formation of a conductive material for a control gate are added to the capping layer. Accordingly, the generation of voids can be prevented in the process of forming the control gate. Consequently, reliability of nonvolatile memory devices can be improved because deterioration of an electrical characteristic can be prevented.
Patent Application
20110159674
