Claims
- 1. A method of manufacturing a semiconductor device, comprising the steps of:
- forming a first insulating layer located on a major surface of a semiconductor substrate and having an opening which reaches said major surface of said semiconductor substrate;
- forming a first conductive layer located in said opening and being in contact with a surface of said first insulating layer;
- forming a second insulating layer above said first conductive layer;
- forming an amorphous silicon layer having a thickness of not more than 0.1 .mu.m and covering at least said second insulating layer to form a lower electrode of a cylindrical capacitor;
- removing said amorphous silicon layer at least from an upper surface of said second insulating layer and thereby exposing said upper surface of said second insulating layer;
- removing said exposed second insulating layer by etching;
- forming a capacitor insulating layer covering said amorphous silicon layer;
- polycrystallizing said amorphous silicon layer to form a polysilicon layer; and
- forming a second conductive layer covering said capacitor insulating layer.
- 2. A manufacturing method of a semiconductor device according to claim 1, wherein said step of forming said amorphous silicon layer includes the step of forming an amorphous silicon layer having a surface roughness of about 10 .ANG. or less, using a CVD method.
- 3. A manufacturing method of a semiconductor device according to claim 1, wherein said step of forming said polysilicon layer includes the step of forming a polysilicon layer having a crystal grain diameter in a range from about 1000 .ANG. to about 10000 .ANG. and a surface roughness of about 10 .ANG. or less.
- 4. A method of manufacturing a semiconductor device, comprising the steps of:
- forming a first insulating layer located on a major surface of a semiconductor substrate and having an opening which reaches said major surface of said semiconductor substrate;
- forming a first conductive layer located in said opening and being in contact with a surface of said first insulating layer;
- forming a second insulating layer above said first conductive layer;
- forming an etching mark on said second insulating layer;
- applying etching to said second insulating layer, using said etching mask as a mask, to remove said second insulating layer at a region, on which said etching mask is not formed, and to further remove said second insulating layer to form an undercut at a region, which is located under a side end of said second insulating layer and is adjacent said first insulating layer;
- forming a second conductive layer covering said second insulating layer after removal of said etching mask;
- removing said residual second insulating layer after patterning said second conductive layer;
- forming a capacitor insulating layer covering said first and second conductive layers; and
- forming a third conductive layer covering said capacitor insulating layer.
- 5. A method of manufacturing a semiconductor device according to claim 4, wherein said step of further removing said second insulating layer to a predetermined extent includes the step of etching said second insulating layer under a condition, in which a density of etching gas plasma is increased, for further removing said second insulating layer.
- 6. A method of manufacturing a semiconductor device according to claim 4, wherein said steps of forming said second conductive layer includes the steps of
- forming an amorphous silicon layer having a surface roughness of about 10 .ANG. or less, using a CVD method; and
- polycrystallizing said amorphous silicon layer for ultimately forming said second conductive layer formed of a polysilicon layer having a crystal grain diameter of about 1000 .ANG.-10000 .ANG. and a surface roughness of about 10 .ANG. or less.
Priority Claims (1)
Number |
Date |
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4-106759 |
Apr 1992 |
JPX |
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Parent Case Info
This application is a continuation of application Ser. No. 08/207,519 filed Mar. 8, 1994, abandoned, which is a division of application Ser. No. 08/008,020 filed Jan. 22, 1993, U.S. Pat. No. 5,315,140.
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5091761 |
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Non-Patent Literature Citations (3)
Entry |
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Divisions (1)
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Number |
Date |
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Parent |
8020 |
Jan 1993 |
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Continuations (1)
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Number |
Date |
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207519 |
Mar 1994 |
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