This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2010-145886, filed on Jun. 28, 2010 the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a method of manufacturing a semiconductor device, a semiconductor device, and a camera module.
The miniaturization and the high integration of a semiconductor element are accelerated. For this reason, generation of a minute foreign material and a defect that is caused by removing or chipping of a stacked film of an end portion of a substrate greatly affects a yield of the product. In order to decrease this influence, bevel polishing to polish the end portion of the substrate with a blade is generally performed.
However, if polishing such as the bevel polishing is performed, a metal such as copper or aluminum to form a circuit may be exposed from a polished portion, and the metal may be contaminated. In particular, in a back surface irradiation type complementary metal oxide semiconductor (CMOS) image sensor that attracts attention in recent years, after bonding two substrates of a device substrate having a copper or aluminum wire and a support substrate, a back surface of the device substrate is mechanically and chemically polished. For this reason, the contamination from the end portion of the substrate may spread over the entire substrate.
According to embodiments, a method of manufacturing a semiconductor substrate includes a polishing process of polishing a peripheral portion of a semiconductor substrate and a protective film forming process of forming a protective film to be an insulating film, on a surface of the semiconductor substrate including a surface exposed by the polishing process.
The semiconductor substrate according to this embodiment may be manufactured using any method of manufacturing a semiconductor. For example, an opening is formed in the semiconductor substrate 1 using resist exposure and etching, the opening is filled with an insulating material such as a silicon oxide film or a silicon nitride film, using a chemical vapor deposition (CVD) method or a coating method, and a semiconductor region 2 is formed using a shallow trench isolation (STI) method. Then, the light receiving element 3, the gate 4, and the source/drain 5 are formed on the silicon substrate 1, deposition of the interlayer insulating film 6 and formation of the aluminum wire 7 are repeated thereon, and a multilayered wire is formed.
In
Next, a method of manufacturing a semiconductor substrate according to this embodiment will be described.
First, trimming processing is performed using bevel polishing to polish a predetermined portion (portion shown by a dotted line in
Next, as illustrated in
By forming the protective film 9, the contamination of metal of the semiconductor substrate can be prevented, even when the metal is exposed by the trimming processing. Even though heat treatment or chemical processing is executed thereafter, the semiconductor substrate can be protected. The thickness of the protective film 9 may be appropriately set according to the material thereof. However, when the Si3N4 film is used, if the thickness of about 50 nm or more is set, the semiconductor substrate can be protected, even though the heat treatment or the chemical processing is executed thereafter. If the Si3N4 film, the PSG film, or the polyimide film is used as the protective film 9, a passivation effect due to the protective film 9 can be expected, and the semiconductor substrate can be protected from external damages and ultraviolet rays.
When the semiconductor substrate is used independently without being bonded to another substrate, after the protective film 9 is formed, the semiconductor substrate is divided and a semiconductor element (semiconductor device) is formed.
Next, a process that is executed when the semiconductor substrate is bonded to the other substrate will be described. For example, the semiconductor substrate that is used in the back surface irradiation type CMOS image sensor is bonded to the other substrate (support substrate), after the process illustrated in
When the semiconductor substrate and another substrate are bonded using an adhesive material, an organic adhesive such as a urethane resin and an epoxy resin may be used as a material of the adhesive layer 10. When direct bonding is used, the SiO2 film and the Si3N4 film may be used as the material of the adhesive layer 10. The thickness of the adhesive layer 10 may be appropriately set according to the material thereof. However, when the SiO2 film using silane or tetraethoxysilane (TEOS) as a material is used, the thickness of the adhesive layer 10 is about 100 nm. Meanwhile, the thickness of the protective film 9 is about 50 nm, when the Si3N4 film using silane and ammonia as a material is used.
As such, in this embodiment, after the end portion of the semiconductor substrate is trimmed, the protective film 9 is formed on the surface of the interlayer insulating film 6 of the semiconductor substrate including the exposed surface 8. For this reason, the contamination of the end portion of the semiconductor substrate can be prevented.
The configuration of the semiconductor substrate illustrated in
After the semiconductor substrate used in the back surface irradiation type CMOS image sensor is bonded to a support substrate, the semiconductor substrate is processed as a chip of the back surface irradiation type CMOS image sensor. The semiconductor substrate is preferably miniaturized to efficiently collect light incident on a back surface in a photodiode. In order to miniaturize the semiconductor substrate, a method that cuts the semiconductor substrate from the back surface after the semiconductor substrate is bonded to the support substrate is used. At this time, in order to cut the semiconductor substrate by chemical and mechanical polishing or chemical processing, the semiconductor substrate that has the stopper layer 11 is used.
As the semiconductor substrate having the stopper layer 11, for example, a silicon on insulator (SOI) substrate may be used. In the case of the SOI substrate, the stopper layer 11 is a silicon oxide layer. As the semiconductor substrate having the stopper layer 11, a substrate that is formed by doping boron, phosphorus, and arsenic in the silicon substrate 1 using an ion injection method may be used. In this case, a doping layer that is formed by doping becomes the stopper layer 11.
In the case of the semiconductor substrate used in the back surface irradiation type CMOS image sensor, before stacking the interlayer insulating film 6, the conductor plug 12 that passes through a portion from the surface of the silicon substrate 1 to the stopper layer 11 is formed in the silicon substrate 1. The conductor plug 12 is a plug to electrically connect the back surface and the front surface thereof.
Next, as illustrated in
Next, as illustrated in
As illustrated in
Then, by attaching a color filter to the stacked substrate and dividing the stacked substrate, a semiconductor element (semiconductor device) is formed.
By combining the semiconductor element 18 formed in the above-described way with a lens module, the back surface irradiation type CMOS image sensor is formed.
As such, in this embodiment, when the substrate having the stopper layer 11 is used as the semiconductor substrate, the semiconductor substrate is trimmed and the protective film 9 is formed on the surface of the interlayer insulating film 6 of the semiconductor substrate including the exposed surface 8. As a result, the same effect as that of the first embodiment can be obtained, and the interlayer insulating film 6 can be prevented from being etched when the chemical processing to remove the stopper layer 11 is executed.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Number | Date | Country | Kind |
---|---|---|---|
2010-145886 | Jun 2010 | JP | national |
Number | Name | Date | Kind |
---|---|---|---|
5426073 | Imaoka et al. | Jun 1995 | A |
6583029 | Abe et al. | Jun 2003 | B2 |
7122095 | Letertre et al. | Oct 2006 | B2 |
7404870 | Letertre et al. | Jul 2008 | B2 |
7859073 | Matsuo et al. | Dec 2010 | B2 |
7989907 | Inoue | Aug 2011 | B2 |
8093687 | Letertre et al. | Jan 2012 | B2 |
8288710 | Tsukamoto et al. | Oct 2012 | B2 |
20030008478 | Abe et al. | Jan 2003 | A1 |
20090117707 | Shimomura et al. | May 2009 | A1 |
20090295979 | Matsuo et al. | Dec 2009 | A1 |
20100019134 | Tsukamoto et al. | Jan 2010 | A1 |
20100096677 | Inoue | Apr 2010 | A1 |
20100255682 | Trickett et al. | Oct 2010 | A1 |
20110073983 | Tanida et al. | Mar 2011 | A1 |
Number | Date | Country |
---|---|---|
2000-252354 | Sep 2000 | JP |
2000-340544 | Dec 2000 | JP |
2004-55750 | Feb 2004 | JP |
2007-96091 | Apr 2007 | JP |
2007-214256 | Aug 2007 | JP |
2007-305755 | Nov 2007 | JP |
2009-99875 | May 2009 | JP |
2009-224496 | Oct 2009 | JP |
Entry |
---|
Notice of Rejection issued by the Japanese Patent Office on Sep. 24, 2013, for Japanese Patent Application No. 2010-145886, and English-language translation thereof. |
Notice of Rejection issued by the Japanese Patent Office on Dec. 17, 2013, for Japanese Patent Application No. 2010-145886, and English-language translation thereof. |
First Examination Opinion issued by the Taiwanese Patent Office on Aug. 29, 2013, for Taiwanese Patent Application No. 100119277, and English-language translation thereof. |
Number | Date | Country | |
---|---|---|---|
20110317050 A1 | Dec 2011 | US |