1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a gate electrode used in a transistor.
2. Description of the Related Art
A memory cell of a DRAM (Dynamic Random Access Memory) (hereinafter referred to as “DRAM cell”) as a typical example of conventional semiconductor device will briefly be described below. A conventional DRAM is disclosed in FIG. 19 of Japanese laid-open patent publication No. 2003-17586 (hereinafter referred to as “Patent Document 1”).
An n-type buried well layer (not shown) is disposed in a silicon substrate, and p-type well layer 3 to which a substrate potential is applied is disposed in the surface of the n-type buried well layer which faces the silicon substrate. The cell transistor has an active region disposed in the surface of p-type well layer 3 which faces the silicon substrate. The active region is surrounded by a groove-like device isolating region in which insulating layer 2 is buried, and p-type channel doped layer 4 for setting a threshold voltage is disposed in the surface of the active region.
Gate electrodes 6 are disposed over the active region with gate oxide film 7, which serves as a gate insulating film, interposed there between. Regions of the active area over which gate electrodes 6 are not disposed include n-type low-concentration diffused layers 9 which will serve as source and drain electrodes. One of n-type low-concentration diffused layers 9 is connected to a lower electrode of a capacitor 10 through plug 5 and plug 11. Another n-type low-concentration diffused layer is connected to bit line 1 through plug 5. Gate electrodes 6 serve as word lines. As shown in
Each of gate electrodes 6 is of a laminated structure including phosphorus-doped polycrystalline silicon film 66 and tungsten silicide film 63. Protective film 27 is disposed on gate electrodes 6. Side spacers 8 are disposed on opposite side walls of each of gate electrodes 6 for insulating plugs 5 and gate electrodes 6 from each other. Silicon oxide films 44 are interposed between gate electrodes 6 and side spacers 8 for increasing the withstand voltages of the gate oxide films.
Interlayer insulating film 12 is disposed on protective film 27, and interlayer insulating films 13, 14 are successively disposed on interlayer insulating film 12. Plugs 5 are placed in respective openings extending from interlayer insulating film 12 to the surfaces of n-type low-concentration diffused layers 9. Bit line 1 is connected to plug 5 through an opening defined in interlayer insulating film 13. Plugs 11 are placed in respective openings defined in interlayer insulating films 13, 14.
In the structure shown in
A fabrication process from the formation of the n-type buried well layer to the formation of n-type low-concentration diffused layers 9 of the cell transistor for manufacturing the DRAM cell shown in
A silicon oxide film is formed on the surface of a silicon substrate, and as shown in
Then, boron ions are implanted at 10 keV with 7E12/cm2 to form p-type channel doped layer 4. After the silicon oxide film on the surface of the silicon substrate is removed, gate oxide film 7 is formed by thermal oxidation. The heat treatment for forming gate oxide film 7 also activate the boron of p-type channel doped layer 4. Then, phosphorus-doped polycrystalline silicon film 66 is deposited to about 100 nm, and then tungsten silicide film 63 is deposited to about 150 nm on phosphorus-doped polycrystalline silicon film 66, thereby forming the material of gate electrodes 6 as a two-layer film. Thereafter, a silicon oxide film and a silicon nitride film are deposited as protective film 27 for gate electrode processing on tungsten suicide film 63. However, protective film 27 may comprise an insulating film other than a silicon oxide film and a silicon nitride film.
After a resist having a predetermined pattern is formed by lithography, the assembly is subjected to anisotropic dry etching from above the resist, thereby removing protective film 27, tungsten silicide film 63, and phosphorus-doped polycrystalline silicon film 66 in areas not covered with the resist, thereby forming gate electrodes 6. At this time, the surface of gate oxide film 7 is exposed. The anisotropic dry etching is performed under conditions to leave gate oxide film 7 unremoved.
After the resist is removed, the sides of gate electrodes 6 are oxidized by thermal oxidation to form silicon oxide films 44 thereon. At this time, the areas of gate oxide film which were exposed to the anisotropic dry etching for forming gate electrodes 6 have their thickness increased. For forming silicon oxide films 44, the sides of gate electrodes 6 are oxidized by thermal oxidation at 1050° C. for several tens of seconds in a dry oxygen atmosphere in order for a bare silicon substrate for measuring the thickness of a grown film to have an oxide film thickness in the range from 4 to 7 nm. Thereafter, phosphorus ions are implanted at 10 keV with 2E13/cm2 to form n-type low-concentration diffused layers 9 which will serve as source and drain electrodes. The assembly is then heated for activating the implanted phosphorus. The heat treatment for activating the implanted phosphorus may be performed on n-type low-concentration diffused layers 9 of the cell transistor, or may be performed at the time low-concentration diffused layers in peripheral transistors disposed around the memory cell block are activated. At any rate, the heat treatment is performed at 900 to 1000° C. for several tens of seconds in a nitrogen atmosphere.
The conventional semiconductor device described above suffers at least two problems to be described below.
The first problem is that since the sides of gate electrodes 6 are oxidized at 1050° C. for forming silicon oxide films 44 thereon, the processed surfaces of tungsten silicide film 63, which serves as a material of gate electrodes 6, tend to cause an increased tungsten contamination, which increases a junction leakage current. In DRAMs, an increased junction leakage current shortens an data retention time. Reasons for such an increased tungsten contamination will be described below.
As shown in
As shown in
The second problem is that at the above temperature for oxidizing the sides of gate electrode 6, the grain growth of tungsten silicide film 63 is so insufficient that the layer resistance thereof is not sufficiently lowered. If the layer resistance of tungsten silicide film 63 is high, then gate electrode 6 has a high resistance itself. If gate electrode 6 of high resistance is used as a word line in a DRAM, then the operation of the DRAM is slow because of an interconnection delay. Though various heat treatments are performed after the side oxidization, they are unable to sufficiently lower the layer resistance of tungsten silicide film 63 because the temperatures of those various heat treatments are lower than the side oxidization temperature.
The relationship between the heat treatment temperature and the layer resistance of the tungsten silicide film will be described below.
The relationship between the heat treatment temperature and the scattered amount of tungsten (W).
As described above, there is a trade-off between the tungsten contamination and the layer resistance of the tungsten silicide film upon the side oxidization of gate electrodes 6. As a consequence, the oxidization temperature cannot easily be changed.
It is an object of the present invention to provide a method of manufacturing a semiconductor device to prevent a junction leakage current from increasing and also to reduce the layer resistance of a gate electrode.
According to the present invention, a method of manufacturing a semiconductor device comprises the steps of forming a gate electrode made of a material containing a refractory metal, then oxidizing the gate electrode to form an oxide film for covering an exposed side surface of the gate electrode, at a predetermined temperature in an initial oxidization phase, and thereafter, oxidizing the gate electrode at a temperature higher than the predetermined temperature in an additional oxidization phase.
Since the side surface of the gate electrode is covered with the oxide film in the initial oxidization phase, the refractory metal is prevented from being scattered from the side surface of the gate electrode in the additional oxidization phase. The layer resistance of the film containing the refractory metal is reduced because the additional oxidization phase is performed at the higher temperature. Therefore, upon side oxidization after the gate electrode of a MOS transistor or the like is processed, a refractory metal contamination from the gate electrode is reduced to prevent a junction leakage current from increasing, and the layer resistance of the film containing the refractory metal is reduced to increase the operating speed of the transistor.
The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of the present invention.
A method of manufacturing a semiconductor device according to the present invention resides in that when an oxide film is formed by thermal oxidization on the side walls of a gate electrode of a transistor used in a semiconductor device, the thermal oxidization is performed at a lower temperature in an initial stage thereof and thereafter performed at a higher temperature. Processing details for forming the oxide film will be described in detail below.
As shown in
According to the temperature sequence shown in
A process of forming a silicon oxide film on a side wall of a gate electrode of a transistor according to a thermal oxidization process based on the temperature sequence shown in
As shown in
Temperature conditions for the initial oxidization phase will be described in detail below. In the initial oxidization phase, as shown in
A lower limit for the oxidized amount of material in the initial oxidization phase will be described below. The amount of material oxidized in the initial oxidization phase needs to be in the range from 1 to 3 nm in terms of film thickness so that the contamination due to diffused tungsten in the subsequent high-temperature additional oxidization phase may be small. With respect to the lower limit for the oxidized amount of material in the initial oxidization phase, a film thickness of about 1 nm or greater is capable of preventing the silicon substrate from being oxidized as the diffusion of tungsten into the silicon oxide film is relatively slow. As shown in
An upper limit for the oxidized amount of material in the initial oxidization phase will be described below. Since oxidization goes on below the gate electrode if the oxidized amount of material grows in the initial oxidization phase, it is necessary to set an upper limit for the oxidized amount of material in order to prevent oxidization from progressing below the gate electrode. If the assembly is oxidized at a temperature lower than 1050° C., then the difference between the oxidized rates of phosphorus-doped poly crystalline silicon film 66 and the semiconductor substrate below gate oxide film 66 which is exposed after the gate electrode is processed, increases, and the oxidized amount of phosphorus-doped polycrystalline silicon film 66 becomes relatively greater. Therefore, the oxidized amount of the lower portion of the gate electrode below phosphorus-doped polycrystalline silicon film 66 is increased. If the oxidized amount of the lower portion of the gate electrode becomes too large, gate oxide film 7 at an end of the lower portion of the gate electrode becomes effectively thick. As a result, the threshold voltage of the transistor rises. If the film thickness of the gate oxide film below the gate electrode varies, then the threshold voltage of the transistor tends to vary greatly. The oxidized amount of material which will not give rise to the above problem should preferably be 3 nm or smaller in terms of film thickness in the initial oxidization phase.
Temperature conditions for the additional oxidization phase will be described in detail below. The temperature in the additional oxidization phase needs to be 1050° C. or higher for sufficiently lowering the layer resistance of tungsten silicide film 63, as shown in
The oxidized amount of material in the additional oxidization phase will be described below. As shown in
A process of fabricating a cell transistor for use in a DRAM according to an embodiment of the present invention will be described below.
As shown in
After silicon oxide film 23 is removed, gate oxide film 24 having a thickness of 7 nm is formed by thermal oxidization. Phosphorus-doped polycrystalline silicon film 25 having a thickness of 70 nm and tungsten silicide film 26 having a thickness of 100 nm are formed on gate oxide film 24. Then, a laminated film structure including a silicon oxide film having a thickness of 30 nm and a silicon nitride film having a thickness of 150 nm are formed as protective film 27 on tungsten silicide film 26 (see
A resist having a predetermined pattern is formed by lithography on protective film 27. Thereafter, the assembly is subjected to anisotropic dry etching from above the resist, thereby removing protective film 27, tungsten silicide film 26, and phosphorus-doped polycrystalline silicon film 25 in areas not covered with the resist. Then, the resist is removed. As shown in
Then, as shown in
After silicon oxide films 29 are formed on the side walls of gate electrodes 6, phosphorus ions are implanted at 15 keV with 9E12/cm2 and at 10 keV with 9E12/cm2 to form n-type low-concentration diffused layers 9 which will serve as source and drain electrodes. Subsequently, the assembly is heated at 1000° C. for 10 seconds in a nitrogen atmosphere (see
Then, after silicon nitride film 31 having a thickness of 50 nm and silicon oxide film 32 having a thickness of 300 nm are formed, the surface of silicon oxide film 32 is planarized by etching back and CMP (Chemical and Mechanical Polishing), for example. Then, a resist having a predetermined opening pattern is formed on silicon oxide film 32 by lithography in order to form openings to be filled by plugs. Thereafter, the assembly is subjected to anisotropic dry etching from above the resist, thereby forming plug openings 40 extending from silicon oxide film 32 to n-type low-concentration diffused layers 9, after which the resist is removed (see
Then, phosphorus ions are implanted for electric field relaxation and arsenic ions are implanted for reducing the diffused layer resistance. The phosphorus ions are implanted at 30 keV with 1E13/cm2, and the arsenic ions are implanted at 20 keV with 2E13/cm2. Between the implantation of the phosphorus ions and the implantation of the arsenic ions, the assembly is heated at 950° C. for 10 seconds in a nitrogen atmosphere. As shown in
Then, after a phosphorus-doped polycrystalline silicon film having a thickness of 100 nm is formed, the phosphorus-doped polycrystalline silicon film is removed by etching back until silicon oxide film 32 is exposed. Now, as shown in
Thereafter, bit line 1 is formed in the same manner as with the conventional process, and then interlayer insulating film 14 is formed. After plugs 11 are formed, capacitors 10 are formed, thereby producing a DRAM cell as shown in
Data retention characteristics of the DRAM fabricated by the method according to the present invention will be described in comparison with those of a DRAM fabricated by the conventional process will be described below.
As shown in
As described above, the principles of the present invention as they are applied to a cell transistor for a DRAM are capable of improving the data retention characteristics of the DRAM. Moreover, the layer resistance of the tungsten silicide films of the gate electrodes is reduced thereby to increase the operating speed of the transistor, allowing the DRAM to operate more quickly.
As the data retention characteristics of the DRAM are improved, the refresh cycle is extended to reduce electric power that is consumed by charging and discharging data. Furthermore, since the power consumption is reduced, the present invention is applicable to the fabrication of semiconductor devices for use in cellular phones and semiconductor devices for use in apparatus that operate at high temperatures.
The refractory metal for use as the material of the gate electrodes is not limited to tungsten, but may be titanium, tantalum, molybdenum, or the like.
While a preferred embodiment of the present invention has been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the following claims.
Number | Date | Country | Kind |
---|---|---|---|
2004-346016 | Nov 2004 | JP | national |