Claims
- 1. A method of fabricating a semiconductor memory device, including: a memory array portion formed on a semiconductor substrate at a first location of one main surface thereof and including a plurality of MIS memory transistors, said MIS memory transistors being respectively formed at first areas of said first location and each having a floating gate electrode and a control gate electrode overlying said floating gate electrode; and a peripheral circuit portion formed at a second location of said semiconductor substrate different from said first location in association with said memory array portion and including a plurality of MIS transistors and wiring lines, said wiring lines being respectively formed at second areas of said second location, comprising the steps of:
- forming a first insulating film on said semiconductor substrate at said first location and said second location;
- forming a first layer of conductive material on said first insulating film at said first location;
- forming a second insulating film on said first layer of conductive material;
- forming a second layer of conductive material on said second insulating film at said first location and on said first insulating film at said second location;
- patterning said second layer of conductive material, said second insulating film, said first layer of conductive material and said first insulating film at said first location using a photoresist film as a mask so as to form said control gate electrode and said floating gate electrode of said memory array portion; and
- separately, at a different time, patterning said second layer of conductive material at said second location so as to form at least some of said gates and some of said wiring lines.
- 2. The method according to claim 1, and further including the step of: also forming said first layer of conductive material on said first insulating film at said second location; and patterning said first layer of conductive material on said first insulating film at said second location so as to form other of said gate electrodes.
- 3. The method according to claim 1 or 2, and further including patterning said first layer of conductive material to form some of said wiring lines.
- 4. The method according to claim 1, wherein said second layer of conductive material comprises a polycrystalline silicon layer.
- 5. The method according to claim 2, comprising forming said first and second polycrystalline silicon layers by the chemical vapor deposition method.
- 6. The method according to claim 5, wherein said first and second conductive layers are approximately 3500 .ANG. thick.
- 7. The method according to claim 6, wherein said first and second layers of conductive material are doped with phosphorous.
- 8. The method according to claim 1, and further including depositing a phosphosilicate glass film over said substrate and patterning said film with contact holes.
- 9. The method according to claim 8, and further including forming a further patterned layer of conductive material over said phosphosilicate glass film and extending through said holes to form a further wiring layer.
- 10. A method of fabricating a semiconductor memory device, including: a memory array portion formed on a semiconductor substrate at a first location of one main surface thereof and including a plurality of MIS memory transistors, said MIS memory transistors being respectively formed at first areas of said first location and each having a floating gate electrode; and a peripheral circuit portion formed at a second location of said semiconductor substrate different from said first location in association with said memory array portion and including a plurality of MIS transistors and wiring lines, said wiring lines being respectively formed at second areas of said second location, comprising the steps of:
- forming first insulating films on said semiconductor substrate at said first location;
- forming a first layer of conductive material on said first insulating film at said first location;
- forming a second insulating film on said first layer of conductive material;
- forming a third insulating film on said second location;
- forming a second layer of conductive material on said second insulating film at said first location on said third insulating film at said second location;
- patterning said second layer of conductive material, said second insulating film, said first layer of conductive material and said first insulating film at said first location using a photoresist film as a mask so as to form said control gate electrode and said floating gate electrode of said memory array portion; and
- separately, at a different time, patterning said second layer of conductive material at said second location so as to form at least some of said gates and some of said wiring lines.
- 11. The method according to claim 10, and further including: also forming said first insulating film and said first layer of conductive material on said first insulating films at said second location; and patterning said first layer of conductive material on said first insulating film at said second location so as to form other of said gate electrodes.
- 12. The method according to claim 10 or 11, and further including patterning of first layer of conductive material to form some of said wiring lines.
- 13. The method according to claim 10, wherein said second layer of conductive material comprises a polycrystalline silicon layer.
- 14. The method according to claim 11, comprising forming said first and second polycrystalline silicon layers by the chemical vapor deposition method.
- 15. The method according to claim 14, wherein said first and second conductive layers are approximately 3500 .ANG. thick.
- 16. The method according to claim 15, wherein said first and second layers of conductive material are doped with phosphorus.
- 17. The method according to claim 10, and further including depositing a phosphosilicate glass film over said substrate and patterning said film with contact holes.
- 18. The method according to claim 17, and further including forming a further patterned layer of conductive material over said phosphosilicate glass film and extending through said holes to form a further wiring layer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
55-18983 |
Feb 1980 |
JPX |
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Parent Case Info
This application is a continuation of application Ser. No. 668,675, filed Nov. 5, 1984, which is a division of Ser. No. 428,954, filed Sept. 30, 1982, both now abandoned.
US Referenced Citations (6)
Divisions (1)
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Number |
Date |
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Parent |
428954 |
Sep 1982 |
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Continuations (1)
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Number |
Date |
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Parent |
668675 |
Nov 1984 |
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