Patent Application
20200335394
The present invention relates to a method of manufacturing a substrate and the same substrate.
It is common practice to form a wire in a fine wiring groove, a hole or a resist opening formed in a surface of a substrate, such as a semiconductor wafer, or form a bump (protruding electrode) to be electrically connected to an electrode or the like of a package on a surface of a substrate. As a process of forming such a wire or bump, electrolytic plating, vapor deposition, printing, and ball bumping are known, for example. In recent years, with the increase in number of I/Os and the decrease in pitch of semiconductor chips, the electrolytic plating, which is ready for miniaturization and is relatively stable in performance, has become more commonly used.
When the electrolytic plating is used to form a wire or a bump, a seed layer (power supply layer) having low electric resistance is formed on a surface of a barrier metal that is formed in a wiring groove, a hole or a resist opening in the substrate (see PTL1, for example).
PTL1: Japanese Patent Laid-Open No. 2014-60379
Such a electrolytic plating is used for manufacturing a substrate that has a bump at a resist opening.
As shown in
As shown in
The temperature of the resist layer 202 is affected by the temperature of the plating solution used when the copper wiring layer 203 is formed and the temperature of the plating solution used when the barrier layer 204 is formed. That is, when the copper wiring layer 203 is formed, the temperature of the resist layer 202 is close to approximately 25° C., which is the temperature of the plating solution used when the copper wiring layer 203 is formed. When the barrier layer 204 is formed, the temperature of the resist layer 202 is close to approximately 40° C., which is the temperature of the plating solution used when the barrier layer 204 is formed. When the barrier layer 204 is formed, the resist layer 202 is at a higher temperature than when the copper wiring layer 203 is formed, and therefore thermally expands. As a result of the thermal expansion of the resist layer 202, as shown in
As shown in
The resist layer 202 is then removed by a resist stripping device, and the seed layer 201 is etched into a more appropriate shape by an etching device. As shown in
If the barrier layer 204 has a smaller width than the copper wiring layer 203, when the tin alloy bump layer 205 is reflowed, as shown in
The present invention has been devised in view of the circumstances described above. An object of the present invention is to prevent a tin alloy from coming into contact with a copper wiring layer when a tin alloy bump layer is reflowed.
According to an aspect of the present invention, a method of manufacturing a substrate having a bump at a resist opening is provided. The manufacturing method includes a step of forming a copper wiring layer on the substrate by plating with a plating solution at a first temperature, a step of forming a barrier layer on the copper wiring layer by plating with a plating solution at a second temperature that is approximately equal to the first temperature, and a step of forming a tin alloy bump layer on the barrier layer by plating.
According to this aspect, the barrier layer formed on the copper wiring layer is formed by plating at a temperature approximately equal to the temperature at the time when the copper wiring layer is formed by plating. Therefore, the width of the resist opening at the time when the barrier layer is formed by plating is close to the width of the resist opening at the time when the copper wiring layer is formed by plating. As a result, the width of the barrier layer is close to the width of the copper wiring layer, and when the tin alloy bump layer is reflowed, the tin alloy can be prevented from flowing down to and coming into contact with the copper wiring layer.
According to an aspect of the present invention, the difference between the first temperature and the second temperature is less than 5° C.
According to this aspect, since the difference between the first temperature and the second temperature is less than 5° C., the width of the barrier layer is close to the width of the copper wiring layer, and when the tin alloy bump layer is reflowed, the tin alloy can be prevented from flowing down to and coming into contact with the copper wiring layer.
According to an aspect of the present invention, the difference between the first temperature and the second temperature is 2.5° C. or less.
According to this aspect, since the difference between the first temperature and the second temperature is less than 2.5° C., the width of the barrier layer is even closer to the width of the copper wiring layer, and when the tin alloy bump layer is reflowed, the tin alloy can be prevented with higher reliability from flowing down to and coming into contact with the copper wiring layer.
According to an aspect of the present invention, the difference between the first temperature and the second temperature is 1° C. or less.
According to this aspect, since the difference between the first temperature and the second temperature is less than 1° C., the width of the barrier layer is substantially equal to the width of the copper wiring layer, and when the tin alloy bump layer is reflowed, the tin alloy can be prevented with even higher reliability from flowing down to and coming into contact with the copper wiring layer.
According to an aspect of the present invention, the barrier layer contains one or more metals selected from a group consisting of Ni and Co.
According to this aspect, since the barrier layer is made of a material into which copper of the copper wiring layer is hard to diffuse, the copper of the copper wiring layer can be prevented from diffusing into the tin alloy of the tin alloy bump layer. Typically, the layer of Ni or Co can be formed by electrolytic plating.
According to an aspect of the present invention, a method of manufacturing a substrate having a bump at a resist opening is provided. The method of manufacturing a substrate includes a step of forming a copper wiring layer on the substrate by plating with a plating solution at a first temperature, a step of forming an enhanced barrier layer on the copper wiring layer by plating with a plating solution at a second temperature that is lower than the first temperature, and a step of forming a tin alloy layer on the enhanced barrier layer by plating.
According to this aspect, the enhanced barrier layer on the copper wiring layer is formed by plating at a temperature lower than the temperature at the time when the copper wiring layer is formed by plating. Therefore, the width of the resist opening at the time when the enhanced barrier layer is formed by plating is greater than the width of the resist opening at the time when the copper wiring layer is formed by plating. Therefore, the width of the enhanced barrier layer is greater than the width of the copper wiring layer, and when the tin alloy bump layer is reflowed, the tin alloy can be prevented with higher reliability from flowing down to and coming into contact with the copper wiring layer.
According to an aspect of the present invention, the width of the enhanced barrier layer is greater than the width of the copper wiring layer.
According to this aspect, since the width of the enhanced barrier layer is greater than the width of the copper wiring layer, when the tin alloy bump layer is reflowed, the tin alloy can be prevented with even higher reliability from flowing down to and coming into contact with the copper wiring layer.
According to an aspect of the present invention, the enhanced barrier layer covers at least a part of a side surface of the copper wiring layer.
According to this aspect, since the enhanced barrier layer covers at least a part of a side surface of the copper wiring layer, when the tin alloy bump layer is reflowed, the tin alloy can be prevented with even higher reliability from flowing down to and coming into contact with the copper wiring layer.
According to an aspect of the present invention, the second temperature is lower than the first temperature by 5° C. or more and is equal to or higher than 15° C.
According to this aspect, since the second temperature is lower than the first temperature by 5° C. or more, the width of the enhanced barrier layer can be sufficiently greater than the width of the copper wiring layer. Therefore, the tin alloy can be prevented with higher reliability from coming into contact with the copper wiring layer. Some kinds of plating solution used for forming the enhanced barrier layer by plating contain boric acid. Boric acid can be deposited if the temperature of the plating solution is lower than 15° C. According to this aspect, since the second temperature is equal to or higher than 15° C., boric acid can be prevented from being deposited from the plating solution used for forming the enhanced barrier layer by plating.
According to an aspect of the present invention, the enhanced barrier layer contains one or more metals selected from a group consisting of Ni and Co.
According to this aspect, since the enhanced barrier layer is made of a material into which copper of the copper wiring layer is hard to diffuse, the copper of the copper wiring layer can be prevented from diffusing into the tin alloy of the tin alloy bump layer. Typically, the layer of Ni or Co can be formed by electrolytic plating.
According to an aspect of the present invention, the step of forming the tin alloy bump layer by plating includes a step of forming the tin alloy bump layer with a plating solution at a third temperature that is equal to or higher than the second temperature.
According to this aspect, the tin alloy bump layer is formed by plating at the third temperature that is equal to or higher than the second temperature. Therefore, the width of the resist opening at the time when the tin alloy bump layer is formed by plating is equal to or smaller than the width of the resist opening at the time when the enhanced barrier layer is formed by plating. Therefore, the width of the tin alloy bump layer is equal to or smaller than the width of the enhanced barrier layer, and when the tin alloy bump layer is reflowed, the tin alloy can be prevented from flowing beyond the enhanced barrier layer and from flowing down to and coming into contact with the copper wiring layer.
According to an aspect of the present invention, a substrate having a bump at a resist opening is provided. The substrate includes a copper wiring layer provided on the substrate, an enhanced barrier layer provided on the copper wiring layer, and a tin alloy bump layer on the enhanced barrier layer. The width of the enhanced barrier layer is greater than the width of the copper wiring layer.
According to this aspect, since the width of the enhanced barrier layer is greater than the width of the copper wiring layer, when the tin alloy bump layer is reflowed, the tin alloy can be prevented from flowing down to and coming into contact with the copper wiring layer.
According to an aspect of the present invention, the enhanced barrier layer covers at least a part of a side surface of the copper wiring layer.
According to this aspect, since the enhanced barrier layer covers at least a part of a side surface of the copper wiring layer, when the tin alloy bump layer is reflowed, the tin alloy can be prevented with higher reliability from flowing down to and coming into contact with the copper wiring layer.
According to an aspect of the present invention, the enhanced barrier layer contains one or more metals selected from a group consisting of Ni and Co.
According to this aspect, since the enhanced barrier layer is made of a material into which copper of the copper wiring layer is hard to diffuse, the copper of the copper wiring layer can be prevented from diffusing into the tin alloy of the tin alloy bump layer. Typically, the layer of Ni or Co can be formed by electrolytic plating.
In the following, a first embodiment of the present invention will be described with reference to the drawings. In the drawings described below, the same or equivalent components are denoted by the same reference numerals, and redundant descriptions thereof will be omitted.
The load/unload unit 170A includes two cassette tables 102, an aligner 104 that orients an orientation flat or a notch of the substrate in a predetermined direction, and a spin rinse dryer 106 that dries the plated substrate by spinning the same at high rate. A cassette 100 that houses the substrate, such as a semiconductor wafer, is mounted on the cassette table 102. A substrate attaching/detaching unit 120 on which the substrate holder 40 is mounted for attaching or detaching of the substrate is provided near the spin rinse dryer 106. At the center of the units 100, 104, 106 and 120, a substrate transporting device 122, which is constituted by a transporting robot that transfers the substrate between the units, is arranged.
The substrate attaching/detaching unit 120 is provided with a flat mount plate 152 that is slidable in a horizontal direction on a rail 150. Two substrate holders 40 are mounted on the mount plate 152 in a horizontal position side by side. After a substrate is transferred between one of the substrate holders 40 and the substrate transporting device 122, the mount plate 152 is slid in the horizontal direction, and a substrate is transferred between the other substrate holder 40 and the substrate transporting device 122.
The processing unit 170B of the plating apparatus includes a stocker 124, a pre-wet bath 126, a pre-soak bath 128, a first cleaning bath 130a, a blow bath 132, a second cleaning bath 130b, and a plating bath 10. The stocker 124 keeps and temporarily stores the substrate holders 40. In the pre-wet bath 126, the substrate is immersed in pure water. In the pre-soak bath 128, an oxide film on a surface of a conductive layer, such as a seed layer, formed on a surface of the substrate is removed by etching. In the first cleaning bath 130a, the pre-soaked substrate and the substrate holder 40 are cleaned with a cleaning solution (such as pure water). In the blow bath 132, draining of the cleaned substrate is performed. In the second cleaning bath 130b, the substrate plated and the substrate holder 40 are cleaned with a cleaning solution. The stocker 124, the pre-wet bath 126, the pre-soak bath 128, the first cleaning bath 130a, the blow bath 132, the second cleaning bath 130b and the plating bath 10 are arranged in this order.
The plating bath 10 has a plurality of plating cells 50 provided with an overflow bath 54, for example. Each plating cell 50 is designed to house one substrate. The substrate is immersed in a plating solution held in the plating cell to plate the surface of the substrate. Specifically, the plurality of plating cells 50 include any one type selected from among a copper plating cell for forming the copper wiring layer described later, a nickel plating cell for forming the barrier layer described later, and a tin-silver plating cell for forming the tin alloy bump layer described later. As described later with reference to
The plating apparatus has a substrate holder transporting device 140 that adopts a linear motor system, for example. The substrate holder transporting device 140 is arranged at the side of the components of the plating apparatus described above and transfers the substrate holder 40 with the substrate between the components. The substrate holder transporting device 140 has a first transporter 142 and a second transporter 144. The first transporter 142 is configured to transfer the substrate between the substrate attaching/detaching unit 120, the stocker 124, the pre-wet bath 126, the pre-soak bath 128, the first cleaning bath 130a and the blow bath 132. The second transporter 144 is configured to transfer the substrate between the first cleaning bath 130a, the second cleaning bath 130b, the blow bath 132 and the plating bath 10. In another embodiment, the plating apparatus may include only one of the first transporter 142 and the second transporter 144.
On the opposite sides of the overflow bath 54, paddle driving devices 19 are arranged that drive paddles 18 (see
As shown in
The anode holder 20 holding the anode 21 and the substrate holder 40 holding the substrate W are immersed in the plating solution Q in the plating processing bath 52 and positioned with the anode 21 and a surface W1 to be plated of the substrate W being opposed to each other and substantially in parallel with each other. In the state where the anode 21 and the substrate W are immersed in the plating solution Q in the plating processing bath 52, a voltage is applied to the anode 21 and the substrate W by a plating power supply 90. Then, metal ions on the surface W1 to be plated of the substrate W are reduced, and a film is formed on the surface W1 to be plated. In the vicinity of the substrate W, a thermometer 59 that measures the temperature of the plating solution Q is arranged. The temperature measured by the thermometer 59 is transmitted to a controller (not shown) and fed back for controlling the plating cell 50.
The plating processing bath 52 has a plating solution supply port 56 for supplying the plating solution Q into the bath. The overflow bath 54 has a plating solution discharge port 57 for discharging an overflow of the plating solution Q from the plating processing bath 52. The plating solution supply port 56 is arranged in the bottom of the plating processing bath 52, and the plating solution discharge port 57 is arranged in the bottom of the overflow bath 54.
As the plating solution Q is supplied to the plating processing bath 52 through the plating solution supply port 56, the plating solution Q overflows from the plating processing bath 52 into the overflow bath 54 beyond the partition wall 55. The plating solution Q having flowed into the overflow bath 54 is discharged through the plating solution discharge port 57, and the temperature of the discharged plating solution Q is adjusted to a desired temperature by a temperature adjustment mechanism 58a, such as a heater or a chiller, of a plating solution circulation device 58. The controller (not shown) adjusts the temperature of the plating solution Q by adjusting the output of the temperature adjustment mechanism 58a with a PID control scheme or the like, based on the output of the thermometer 59. The thermometer 59 may be immersed in the plating solution Q as shown in the drawing or provided on the surface of the substrate holder 40 opposite to the substrate W. The plating solution Q adjusted to the desired temperature is passed through a filter 58b or the like of the plating solution circulation device 58 to remove impurities therefrom. The plating solution Q from which impurities have been removed is supplied to the plating processing bath 52 through the plating solution supply port 56 by the plating solution circulation device 58.
The anode holder 20 has an anode mask 25 that regulates an electric field between the anode 21 and the substrate W. The anode mask 25 is a member made of a dielectric material having a substantially planar shape, for example, and is arranged on a front surface of the anode holder 20. That is, the anode mask 25 is arranged between the anode 21 and the substrate holder 40. The anode mask 25 has a first opening 25a through which a current flowing between the anode 21 and the substrate W passes through in a substantially central part thereof The anode mask 25 has an anode mask attachment part 25b that integrally attaches the anode mask 25 to the anode holder 20 at an outer perimeter thereof.
The plating bath 10 further has a regulation plate 30 that regulates the electric field between the anode 21 and the substrate W. The regulation plate 30 is a member made of a dielectric material having a substantially planar shape, for example, and is arranged between the anode mask 25 and the substrate holder 40 (substrate W). The regulation plate 30 has a second opening 30a through which the current flowing between the anode 21 and the substrate W passes through.
Between the regulation plate 30 and the substrate holder 40, the paddle 18 that agitates the plating solution Q in the vicinity of the surface W1 to be plated of the substrate W. The paddle 18 is a member having a substantially rod-like shape and is arranged in the plating processing bath 52 to vertically extend. The paddle 18 is fixed to the paddle driving device 19 at one end thereof. The paddle 18 is horizontally moved along the surface W to be plated of the substrate W by the paddle driving device 19 to agitate the plating solution Q.
According to a method of manufacturing a substrate according to the first embodiment, in the plating cell 50 shown in
As shown in
As shown in
As shown in
After that, the resist layer 302 is removed by a resist stripping device (see
Since the width of the barrier layer 304 is close to the width of the copper wiring layer 303 as described above, when the tin alloy bump layer 305 is reflowed, the reflowed tin alloy bump layer 305 is less likely to flow down along the side surface of the barrier layer 304, compared with the case shown in
As described above, according to the first embodiment, the barrier layer 304 on the copper wiring layer 303 is formed by plating at a temperature approximately equal to the temperature at the time when the copper wiring layer 303 is formed by plating. Therefore, the width of the opening in the resist layer 302 at the time when the barrier layer 304 is formed by plating is close to the width of the opening in the resist layer 302 at the time when the copper wiring layer 303 is formed by plating. As a result, the width of the barrier layer 304 is close to the width of the copper wiring layer 303, and when the tin alloy bump layer 305 is reflowed, the tin alloy can be prevented from flowing to and coming into contact with the copper wiring layer 303. In the conventional process shown in
Although the barrier layer 304 has been described as containing Ni as an example in the first embodiment, the present invention is not limited thereto, and the barrier layer 304 may contain one or more metals selected from a group consisting of Ni and Co. These metals are materials into which copper of the copper wiring layer 303 is hard to diffuse, so that the copper can be prevented from diffusing into the tin alloy bump layer 305. In addition, although the tin alloy bump layer 305 has been described as containing tin and silver as an example in the first embodiment, the present invention is not limited to this, and the tin alloy bump layer 305 may contain tin and silver or tin and copper.
The “temperature approximately equal to a different temperature” in this specification means that the difference between the two temperatures is smaller than 5° C., or preferably equal to or smaller than 2.5° C., or more preferably equal to or smaller than 1° C. If the difference between the first temperature and the second temperature is smaller than 5° C., the width of the barrier layer 304 and the width of the copper wiring layer 303 are sufficiently close to each other, and when the tin alloy bump layer 305 is reflowed, the tin alloy can be prevented from flowing down to and coming into contact with the copper wiring layer 303. If the difference between the first temperature and the second temperature is equal to or smaller than 2.5° C., the width of the barrier layer 304 and the width of the copper wiring layer 303 are even closer to each other, and when the tin alloy bump layer 305 is reflowed, the tin alloy can be prevented with higher reliability from flowing down to and coming into contact with the copper wiring layer 303. Furthermore, if the difference between the first temperature and the second temperature is equal to or smaller than 1° C., the width of the barrier layer 304 and the width of the copper wiring layer 303 are substantially equal to each other, and when the tin alloy bump layer 305 is reflowed, the tin alloy can be prevented with even higher reliability from flowing down to and coming into contact with the copper wiring layer 303.
Next, a method of manufacturing a substrate according to a second embodiment will be described. The method of manufacturing a substrate according to the second embodiment can be performed with the plating apparatus shown in
As shown in
As shown in
In the second embodiment, the temperature of the plating solution used when the enhanced barrier layer 306 is formed (referred to as a second temperature hereinafter) is set to be lower than the first temperature. In other words, according to the method of manufacturing a substrate according to the second embodiment, the enhanced barrier layer 306 is formed by plating at a lower temperature than in the conventional substrate manufacturing process shown in
In addition, since the width of the opening in the resist layer 302 at the time when the enhanced barrier layer 306 is formed by plating is greater than the width of the opening in the resist layer 302 at the time when the copper wiring layer 303 is formed by plating, a fine gap occurs between the side surface of the copper wiring layer 303 and the resist layer 302. As a result, when the enhanced barrier layer 306 is formed by plating, the plating solution Q enters the gap between at least a part of the side surface of the copper wiring layer 303 and the resist layer 302, so that the enhanced barrier layer 306 is also formed by plating on that part of the side surface of the copper wiring layer 303. That is, as shown in
The second temperature is preferably lower than the first temperature by 5° C. or more. If this condition is satisfied, the width of the enhanced barrier layer 306 can be sufficiently greater than the width of the copper wiring layer, and the area of the side surface of the copper wiring layer 303 covered by the enhanced barrier layer 306 can be increased. In addition, the second temperature is preferably equal to or higher than 15° C. Some kinds of plating solution Q used for forming the enhanced barrier layer 306 by plating contain boric acid. Boric acid can be deposited if the temperature of the plating solution Q is lower than 15° C. According to the second embodiment, since the second temperature is equal to or higher than 15° C., boric acid can be prevented from being deposited from the plating solution Q used for forming the enhanced barrier layer 306 by plating.
As shown in
After that, the resist layer 302 is removed by a resist stripping device, and the seed layer 301 is etched into a more appropriate shape by an etching device (see
Since the width of the barrier layer 304 is greater than the width of the copper wiring layer 303 as described above, when the tin alloy bump layer 305 is reflowed, the reflowed tin alloy bump layer 305 is less likely to flow down along the side surface of the barrier layer 304, compared with the case shown in
As described above, according to the second embodiment, the enhanced barrier layer 306 on the copper wiring layer 303 is formed by plating at a temperature lower than the temperature at the time when the copper wiring layer 303 is formed by plating. Therefore, the width of the opening in the resist layer 302 at the time when the enhanced barrier layer 306 is formed by plating is greater than the width of the opening in the resist layer 302 at the time when the copper wiring layer 303 is formed by plating. As a result, the width of the enhanced barrier layer 306 is greater than the width of the copper wiring layer 303, and when the tin alloy bump layer 305 is reflowed, the tin alloy can be prevented with higher reliability from flowing to and coming into contact with the copper wiring layer 303. In addition, in the second embodiment, since the enhanced barrier layer 306 covers at least a part of the side surface of the copper wiring layer 303, when the tin alloy bump layer 305 is reflowed, the tin alloy can be prevented with even higher reliability from coming into contact with the copper wiring layer 303. In the conventional process shown in
Although the enhanced barrier layer 306 has been described as containing Ni as an example in the second embodiment, the present invention is not limited thereto, and the enhanced barrier layer 306 may contain one or more metals selected from a group consisting of Ni and Co. These metals are materials into which copper of the copper wiring layer 303 is hard to diffuse, so that the copper can be prevented from diffusing into the tin alloy bump layer 305. In addition, although the tin alloy bump layer 305 has been described as containing tin and silver as an example in the second embodiment, the present invention is not limited to this, and the tin alloy bump layer 305 may contain tin and silver or tin and copper.
Next, a third embodiment of the present invention will be described. According to the third embodiment, the configuration of the plating apparatus differs from the plating apparatus shown in
As shown in the drawing, in the plating apparatus, in a subsequent stage to the blow bath 132, the plating cell 50c provided with the second cleaning bath 130b, the plating cell 50b provided with the second cleaning bath 130b, and the plating cell 50a provided with the second cleaning bath 130b are arranged in this order. The plating cells 50a, 50b and 50c have the same configuration as the plating cell 50 shown in
When the plating apparatus shown in
After the copper wiring layer 303 is formed on the substrate in the plating cell 50a, the substrate is transferred to the second cleaning bath 130b provided for the plating cell 50a and cleaned therein. The temperature of the cleaning solution in the second cleaning bath 130b is preferably equal to the temperature of the plating solution in the subsequent plating cell 50b. If this condition is satisfied, when the substrate is immersed in the plating solution in the plating cell 50b, the temperature of the plating solution can be prevented from decreasing or increasing.
The substrate with the copper wiring layer 303 formed thereon is then transferred to the plating cell 50b. After the barrier layer 304 or the enhanced barrier layer 306 is formed in the plating cell 50b, the substrate is transferred to the second cleaning bath 130b provided for the plating cell 50b and cleaned therein. The temperature of the cleaning solution in the second cleaning bath 130b is preferably equal to the temperature of the plating solution in the subsequent plating cell 50c. If this condition is satisfied, when the substrate is immersed in the plating solution in the plating cell 50c, the temperature of the plating solution can be prevented from decreasing or increasing.
The substrate with the barrier layer 304 or the enhanced barrier layer 306 formed thereon is then transferred to the plating cell 50c. After the tin alloy bump layer 305 is formed in the plating cell 50c, the substrate is transferred to the second cleaning bath 130b provided for the plating cell 50c and cleaned therein. The cleaned substrate is transferred to the blow bath 132, and draining of the substrate is performed. The substrate is then detached from the substrate holder 40 in the substrate attaching/detaching unit 120, dried by the spin rinse dryer 106, and then housed in the cassette 100.
As described above, since the plating apparatus shown in
Although embodiments of the present invention have been described above, the embodiments of the present invention described above are given to facilitate understanding of the present invention but are not intended to limit the present invention. Of course, many modifications or alterations can be made without departing from the spirit of the present invention, and the present invention includes equivalents thereof. In addition, as far as at least some of the problems described above can be solved, or at least some of the effects described above can be achieved, any combination of components described in the claims and the specification is possible, and any of the components can be omitted.
201 seed layer
202 resist layer
203 copper wiring layer
204 barrier layer
205 tin alloy bump layer
301 seed layer
302 resist layer
303 copper wiring layer
304 barrier layer
305 tin alloy bump layer
306 enhanced barrier layer
W substrate
| Number | Date | Country | Kind |
|---|---|---|---|
| 2016-071000 | Mar 2016 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2017/012896 | 3/29/2017 | WO | 00 |
