METHOD OF OPERAND WIDTH REDUCTION TO ENABLE USAGE OF NARROWER SATURATION ADDER

Abstract

An electronic computing circuit for implementing a method for reducing the bit width of two operands from a bit length N to a reduced bit length M, thus, M

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention are illustrated by way of example and is not limited by the shape of the Figures of the drawings in which:

FIG. 1 is a schematic block diagram representation of a prior art chip design architecture processing a “Sum across Instruction” having five 32 bit input operands, including a 3:2 and a subsequent 4:2 compression stage and the subsequent 35-bit adding in a respective 35 bit saturation adder;

FIG. 2 is a schematic block diagram representation corresponding to FIG. 1 illustrating the principle way to use the method and circuits of embodiments of the present invention;

FIG. 3 is a zoom view into the box 20 of the circuit in FIG. 2 illustrating a first circuit alternative of a preferred embodiment of the present invention in the use case of FIGS. 1 and 2;

FIG. 4 is a zoom view into the box 20 of the circuit in FIG. 2 illustrating a second circuit alternative of a preferred embodiment of the present invention in the use case of FIGS. 1 and 2;

FIG. 5 is a table representation illustrating different combinations of the bit settings of the output operands, and the respective VMA result in a 2-complement implementation;

FIG. 6 is a control flow diagram of the inventive method when used for above saturation adders, and

FIG. 7 is a depiction according to FIG. 5 for a different implementation.

Claims

1. An electronic computing circuit processing two N-bit input operands of a bit length N and generating two M-bit output operands of a reduced bit length M, comprising: a) means for receiving said two N-bit operands as an input;b) means for adding the (N-M+1) most significant bits of said two N-bit operands in an auxiliary adder logic; andc) a decision logic processing the add result of said auxiliary adder logic for calculating at least the two most significant bits of reduced-bit-length output operands such that a predetermined post-processing can be correctly performed with said M-bit output operands.

2. The circuit according to claim 1 wherein said means for adding the (N-M+1) most significant bits and said decision logic are implemented within a single unit.

3. A method for reducing the bit width of two operands from a bit length N to a reduced bit length M, comprising the steps of: a) receiving said two N-bit operands as an input;b) adding the (N-M+1) most significant bits of said two N-bit operands separately in an auxiliary adder logic; andc) calculating at least the two most significant bits of reduced-bit-length output operands in a decision logic processing the add result of said auxiliary adder logic, such that a predetermined post-processing can be correctly performed with said output operands.

4. The method according to claim 3, wherein the steps b) and c) are implemented within a single unit.

5. The method according to claim 4, wherein a part of said decision logic handles the following three cases of the auxiliary add result: a) <=−2,b) >=0,c) =−1.

6. The method according to claim 5, wherein a part of said decision logic handles the following three cases of the auxiliary add result: a) <−2,b) >0,c) <=0 and >=−2.

7. The method according to claim 3, wherein said post-processing is an add operation.

8. The method according to claim 3, wherein said post-processing is a saturated add operation.

9. The method according to claim 3, wherein said post-processing is a multiply-add operation.

10. The method according to claim 3, wherein said post processing is performed with a bit length M being a power of 2.

11. The method according to claim 3, wherein the predetermined post-processing is done independently of steps b) and c).

12. A computer system comprising an electronic computing circuit for processing two N-bit input operands of a bit length N and for generating two M-bit output operands of a reduced bit length M, wherein the computing circuit comprises: a) means for receiving said two N-bit operands as an input;b) means for adding the (N-M+1) most significant bits of said two N-bit operands in an auxiliary adder logic; andc) a decision logic processing the add result of said auxiliary adder logic for calculating at least the two most significant bits of reduced-bit-length output operands such that a predetermined post-processing can be correctly performed with said M-bit output operands.

13. The computer system according to claim 12 wherein said means for adding the (N-M+1) most significant bits and said decision logic are implemented within a single unit.

14. The computer system according to claim 12 wherein said decision logic comprises means for handling the following three cases of the auxiliary add result: a) <=−2,b) >=0,c) =−1.

15. The computer system according to claim 12 wherein said decision logic comprises means for handling the following three cases of the auxiliary add result: a) <−2,b) >0,c) <=0 and >=−2.

16. The computer system according to claim 12 wherein said predetermined post-processing can be correctly performed with said M-bit output operands using an add operation.

17. The computer system according to claim 12 wherein said predetermined post-processing can be correctly performed with said M-bit output operands wherein M is a power of 2.

18. The computer system according to claim 12 wherein said predetermined post-processing can be correctly performed with said M-bit output operands using a multiply-add operation.

19. The computer system according to claim 12 wherein said predetermined post-processing can be correctly performed with said M-bit output operands using a saturated add operation.