Patent Application
20120140556
1. Field of the Invention
The invention relates to a method of operating a memory, and more particularly to a method of operating a flash memory.
2. Description of Related Art
Non-volatile memory (NVM) is the hottest memory technology now. In a type of NVM, an oxide-nitride-oxide (ONO) structure with charge-trapping effect is adopted instead of the floating gate structure of the traditional cells. Being easily fabricated and having high density, the NVM with the ONO structure attracts much attention and study from various circles. Such NVM is also referred to as charge-trapping flash memory, wherein the ONO structure within each memory cell can store charges. The charges stored affect the threshold voltage (Vt) of the memory cell and the Vt is sensed to determine the data value.
Currently, the multi-level cell (MLC) capable of storing more than two states has been developed to increase the storage density. The term “multi-level” means that the charging includes multiple potential levels, i.e., multiple Vt values. Thereby, the value of more than one bits can be stored in each memory cell, as shown in
During the programming of a memory cell 10, because a programming voltage is applied to the corresponding word line WL1, the storage site 100a suffers from a program disturbance 104 from the left bit line BL1. Further, as the cell size is reduced to 75 nm and the distance between the word lines is shortened, the storage sites 100a and 100b also suffer from a word line interference 106 from the storage sites of the two cells 10 at the front side and the back side respectively.
Accordingly, this invention provides a method of operating a flash memory, by which the memory is prevented from being affected by the 2nd bit effect, program disturbance and word line interference.
The invention also provides a method of operating a flash memory, which can increase the storage density by 1.5 times as compared to the conventional single-level cell (SLC) or multi-level cell (MLC) memory.
The method of operating a flash memory of this invention is applied to a flash memory with a plurality of storage sites arranged in an array. When a first storage site among the storage sites has 2n program levels, the numbers of program levels of the storage sites neighboring to the first storage site are set to be 2n-1. When a second storage site among the storage sites has 2n-1 program levels, the numbers of program levels of the storage sites neighboring to the second storage site are set to be 2n. Each of the program levels corresponds to a different Vt-distribution.
According to an embodiment of this invention, the flash memory may include a virtual ground memory array or NAND flash memory. The flash memory may include charge-trapping memory cells or floating-gate memory cells. The storage sites are all multi-level cells (MLC), or include multi-level cells (MLC) and single-level cells (SLC). In addition, n may be a positive integer not less than 2, such as 2, 3 or 4.
The operation method of this invention is also applied to a flash memory that includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells each corresponding to one word line and a pair of bit lines. The method includes: setting the numbers of program levels of the storage sites of the cells corresponding to the same word line to be 2n and 2n-1 alternately, and setting the numbers of program levels of the storage sites of the memory cells corresponding to the same bit line to be 2n and 2n-1 alternately. Each program level corresponds to a different Vt-distribution.
According to an embodiment of the invention, the flash memory may include a virtual ground memory array. The memory cells may include charge-trapping memory cells or floating-gate memory cells. The storage sites are all MLCs, or include MLCs and SLCs. In addition, n may be a positive integer not less than 2, such as 2, 3 or 4.
Accordingly, in the operation method of the invention, each storage site having 2n-1 program levels is surrounded by storage sites having 2n program levels, and each storage site having 2n program levels is surrounded by storage sites having 2n-1 program levels. Thereby, the storage density of the flash memory is higher than that of SLC or MLC memory. Further, since the parasitic effects can be reduced, the Vt-distributions of the program levels are maintained separate.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, several embodiments accompanied with figures are described in detail below.
Referring to
In the operation method of the flash memory, the storage sites (e.g., 306b, 300a, 300b and 308a) in the cells (e.g., 30d, 30e and 30f) coupled to the same word line (e.g., WL1) are set to have 2n program levels and 2n-1 program levels alternately, and the storage sites (e.g., 302a, 300a and 304a) in the cells (e.g., 30b, 30e and 30h) coupled to the same bit line (e.g., BL1) are set to have 2n program levels and 2n-1 program levels alternately. Each program level corresponds to a different Vt-distribution.
Since a storage site (e.g., 300a) with 2n program levels is surrounded by storage sites (e.g., 300b, 302a, 304a and 306b) with 2n-1 program levels in this embodiment, the parasitic effects can be reduced and decrease of the program level number is prevented. Meanwhile, a storage site (e.g., 300b) with 2n-1 program levels surrounded by storage sites (e.g., 300a, 302b, 308a and 304b) with 2n program levels can tolerate a larger parasitic capacitance without lowering the program level. In other word, at least a half of the memory cells in the entire flash memory are operated with 2n program levels. Thereby, the storage density can be increased by 1.5 times as compared to conventional memory in SLC or MLC operation.
In the above embodiment of the invention, n may be a positive integer not less than 2, such as 2, 3 or 4. Thus, the storage site 300a of the memory cell 30e is a multi-level cell (MLC), and the other storage site 300b of the memory cell 30e is a single-level cell (SLC) when n is 2, or a multi-level cell (MLC) when n is 3 or more.
Moreover, the flash memory operation method can also be applied to an NAND flash memory.
The operation method of this embodiment is described below. When a storage site (e.g., 508) of a cell (e.g., 50e) has 2n program levels, the number of program levels of the neighboring storage sites (e.g., 502, 506, 510 and 514) is set to 2n-1. When a storage site (e.g., 502) has 2n-1 program levels, the number of program levels of the neighboring storage sites (e.g., 500, 504 and 508) is set to 2n. As a result, when n equals 2, the Vt-distribution of a storage site (e.g., 508) having 2n program levels in
In the operation method of the flash memory shown in
In summary, the spirit of the invention is that a storage site having 2n-1 program levels is surrounded by storage sites having 2n program levels to prevent decrease in the program level number of storage site. Hence, at least a half of the memory cells in the entire flash memory can be operated with 2n program levels, and the flash memory has a higher storage density as compared to conventional memory of SLC or MLC operation. Meanwhile, a storage site with the larger number (2n) of program levels is surrounded by storage sites with the smaller number (2n-1) of program levels to reduce the parasitic effects, so that the Vt-distributions of the program levels are maintained separate from each other.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.
