Patent Application
20250095731
This application claims the priority benefit of Italian Patent Application Number 102023000019332, filed on Sep. 20, 2023, entitled “Method of Operating Phase Change Memories, Corresponding Device and Computer Program Product,” which is hereby incorporated by reference to the maximum extent allowable by law.
The description relates to the field of data storage technologies.
One or more embodiments can be applied to various types of computer storage technologies such as PCM, that is, Phase Change Memory, for instance, ePCM (that is, embedded Phase Change Memory) and/or ePCM NVM (that is, Non-Volatile Memory ePCM).
Phase Change Memories, referred to as PCM, are a type of computer storage technology, that is, memory technology and, generally, a type of non-volatile random-access memory technology that may be embedded in integrated circuit (IC) semiconductor devices.
Usually, PCM operates on a bit-by-bit basis since the heat produced by an electric current flowing through a heating material called phase-change material such as, for instance, a chalcogenide glass, is used to melt and quench the phase-change material, making it amorphous, or to hold such phase-change material in its crystallization temperature range, thereby switching it to a crystalline state.
Therefore, a PCM storage unit may use such phase-change material to store 1-bit of information since the two states of the phase-change material, that is, amorphous or crystalline, are characterized by different resistance values that facilitate distinguishing one of the states from the other, that is, each of the two states corresponds to a different value of a single bit.
Thus, the phase-change material can stably exist in two states:
A PCM storage unit can switch between such two states by differently heating the phase-change material, that is, by applying a current to such phase-change material for a given time for switching to a first state and by applying a current of different value to such phase-change material for a different time for switching to a second state.
For instance, a “set” write operation of a specific cell, that is, setting the cell to a high logic state, may be performed by applying on the phase-change material of such specific cell a current pulse with triangular shape.
Therefore, the current flowing within the PCM cell is increased rapidly up to a certain value, for instance, a value that may heat the respective phase-change material above a crystallization temperature associated to such respective phase-change material but under a melt temperature associated with the same phase-change material, and then is decreased slowly.
For instance, a “reset” write operation of a specific cell, that is, setting the cell to a low logic state, can be performed by applying on the phase-change material of such specific cell a short rectangular current pulse.
Therefore, the current flowing within the PCM cell is increased in a fast way up to a certain value, for instance, a value that may heat the respective phase-change material above the melt temperature associated with such respective phase-change material, and then is decreased after a small time, for instance, 100 ns, in a fast way. For instance, a read operation of a specific cell may involve measuring the resistance value of the phase-change material of the specific cell and the respective state of such specific cell, that is, amorphous or crystalline, by applying thereto a given voltage variation and by measuring the respective current flowing therein.
It is noted that after any write operation, that is, a reset or a set write operation, a write verify operation is usually performed, that is, a read operation used to check the success of a corresponding write operation, and:
Therefore, write verify operations may be:
A single-ended PCM is a type of PCM wherein a single cell corresponds to a single bit (that is, 1 cell/bit).
Read operations in single-ended PCM are performed by using a reference current supplied, for instance, by a reference current generator, and a sense amplifier receiving:
Such sense amplifier is further configured to compare such current received from the PCM cell that is read with such reference current in order to determine the logic level store within such PCM cell that is to be read, that is, its state.
Single-ended PCM architectures are affected by resistance drifts resulting from the relaxation phenomenon of amorphous materials, that is, an intrinsic behavior of the amorphous state of phase-change materials resulting in an increase of their resistance values.
In response to a “reset” write operation, the resistance of the amorphous phase-change material starts increasing over time. Such an increase is a consequence of the relaxation that affects the amorphous state of phase-change materials and results from a rearrangement in the atomic configuration of such amorphous phase-change material over time.
In response to such a reset write operation, the phase-change material is rapidly quenched and its atomic configuration is frozen in a highly stressed state, that is, the amorphous state.
The atomic configuration of the amorphous state of the phase-change material is rearranged over time in a configuration with lower free energy. Such rearrangement is a result of thermally-activated annihilation of trapping centers, for instance, vacancies, dangling bonds, or disorder-induced localized states, and leads to a resistance increase over time.
Thus, the observed resistance drift, that is, an increased resistance value, of the amorphous phase-change material is a result of an intrinsic behavior of such amorphous phase-change material, that is, atomic configuration rearrangements resulting from an attempt of lowering the free energy in such configuration.
Such resistance drift results in a variation of the resistance value of a PCM cell during its life, starting from a minimum resistance value right after a reset write operation, that is, when rearrangements resulting from the relaxation effect are still negligible, and increasing over time.
Therefore, a disadvantage of single-ended PCM architectures is the difficulty of selecting a reference current that is constant during the entire working life of the PCM cell.
In fact, such reference current should desirably:
The relaxation effect impacts on read operations of PCM cells that are in a “reset” state, that is, contain a low logic level, since the resistance of the phase-change material changes over time, making more difficult to select a fixed reference current for read operations.
A possible solution may be the use of two cells per bit PCM architectures as disclosed in patent document US 2009/0161417 A1.
Document US 2009/0161417 A1 discloses two cells per bit PCM architecture (that is, 2 cell/bit), that is, PCM architecture wherein two cells contain a single bit of data and one of the two cells, a complement cell, is programmed to the complementary state of the other of the two cells.
Thus, a bit is determined by reading a bit stored in one of the two cells and comparing it to the one stored in the complement cell.
Thus, in two-cells-per-bit PCM architectures a reference current is not needed since a read operation of any data, that is, a high or low logic state, is based on the stored value of such data in a cell in its direct form, that is, high or low logic state respectively, the stored value of such data in a complement cell in its complemented form, that is, low or high logic state respectively, and on the use of a sense amplifier that is configured to receive at one terminal a current of the “direct” cell that has to be read, that is, containing the data in the direct form, and at the other terminal a current of the associated complement cell, that is, containing the data in the complemented form.
Both the occupied area and the production cost of two-cells-per-bit PCM architectures considerably increase with respect to single-ended PCM architectures, since two cells, instead of a single one, are used to store a single bit.
Solutions that decrease the impact of the resistance drift of single-ended PCM architectures would be beneficial in order to reduce production costs and the required area of PCM architectures without sacrificing PCM durability.
An object of one or more embodiments is to contribute in providing such a solution.
According to one or more embodiments, that object is achieved via a method for performing a PCM write operation having the features set forth in the claims that follow.
One or more embodiments concern a corresponding memory device and a corresponding computer program product loadable in at least one processing circuit (e.g., a computer) and comprising software code portions for executing the steps of the method when the product is run on at least one processing circuit. As used herein, reference to such a computer program product is understood as being equivalent to reference to a computer-readable medium containing instructions for controlling a processing system in order to co-ordinate implementation of the method according to one or more embodiments.
The claims are an integral part of the technical teaching provided in respect of the embodiments.
Solutions as described herein include a method of performing write operations, that is, writing data comprising one or more bits, in a Phase Change Memory, PCM device, the PCM device comprising a first set of cells and a second set of cells configured to be set to a low logic level and to a high logic level, respectively, in response to a write operation comprising reset write operations and/or set write operations.
Success or failure of the set write operation is verified via at least one set verify operation to check if the at least one cell in the second set is set to a high logic level in response to the set write operation.
The set write operation is considered:
Success or failure of a reset write operation is verified via at least one verify operation that may be one or more reset write verify operation(s) out of individual and/or looped reset write verify operations to check if the at least one cell in the first set is set to a low logic level in response to the reset write operation.
The reset write operation is thus considered:
The write operation is considered as failed in response to the reset write operation being considered as failed and/or to the set write operation being considered as failed.
Solutions as described herein facilitate achieving single-ended PCM architectures that minimize, that is, reduce or substantially remove, that is, making it negligible, the impact of the resistance drift of a phase-change material, reducing production costs and the required area of PCM architectures without sacrificing their durability.
One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein:
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.
The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.
The edges of features drawn in the figures do not necessarily indicate the termination of the extent of the feature.
In the ensuing description one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.
Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment.
Moreover, particular configurations, structures, or characteristics may be combined in any adequate way in one or more embodiments.
The headings/references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.
For simplicity and ease of explanation, throughout this description, and unless the context indicates otherwise, like parts or elements are indicated in the various figures with like reference signs, and a corresponding description will not be repeated for each and every figure.
Architectures of Phase Change Memory, PCM devices comprise a first set of cells and a second set of cells configured to be set to a low logic level and to a high logic level, respectively, in response to a write operation comprising both reset write operations and/or set write operations.
It is noted that the first set of cells may be also the empty set, that is, if the data to be written in the PCM memory is composed of bits all set to a high logic level.
Similarly, it is noted that the second set of cells may be also the empty set, that is, if the data to be written in the PCM memory is composed of bits all set to a low logic level.
Such write operations in the PCM device are performed under the control of control unit programmed to operate as discussed in the following so that:
The current distributions IR, IS shown in
Exemplary current distributions IS may be distributions of current ranges RHC,D, RHE comprising currents that may pass through a portion of a PCM array, that is, a group of cells, when the states of the cells comprised therein are set to a high logic state, for instance, to “1”, while exemplary current distributions IR may be distributions of current ranges RLA, RLB comprising currents that may pass through the same portion of the PCM array when the states of the cells comprised therein are set to a low logic state, for instance, to “0”.
For instance, a first current distribution ISC,D of a first current range RHC,D related to a portion of a PCM array, that is, a group of cells, after a set write operation may remain substantially stable over time. For instance, such first current distribution ISC,D may be the same in a first time instant C and a second time instant D, indicating respectively a moment after a given amount of time from a set write operation, for instance, after days, and a moment right after the same set write operation, that is, after a given amount of time that is significantly smaller than the amount of time considered for the first time instant C, for instance, few instants after the set write operation.
In fact, the first current range RHC,D is associated with currents that may pass through a portion of a PCM array when the state of the cells comprised therein is set to a high logic state, that is, when such cells comprised therein are in a crystalline state that is not affected by relaxation and thus characterized by a constant resistance.
Conversely, current distributions associated with a portion of a PCM array, that is, a group of cells, after a reset write operation may vary over time as the respective current ranges RLA, RLB are associated with currents that may pass through a portion of a PCM array when the state of the cells comprised therein is set to a low logic state, that is, when such cells comprised therein are in an amorphous state that is affected by relaxation and thus characterized by a resistance that increases over time.
Therefore, a second current distribution IRA of a second current range RLA obtained in a third time instant A and related to a portion of a PCM array after a reset write operation may be different from a third current distribution IRB of a third current range RLB obtained in a fourth time instant B and related to the same portion of a PCM array after the same reset write operation, wherein the third time instant A indicates a moment after a given amount of time from the reset write operation, that is, when rearrangements resulting from the relaxation effect are affecting the resistance value of the phase-change material of the cells comprised therein of a non-negligible amount and the fourth time instant B indicates a moment right after a reset write operation, that is, when rearrangements resulting from the relaxation effect are still negligible, not affecting the resistance value of the phase-change material of the cells comprised therein, for instance, few instants after the reset write operation.
In fact, in the fourth time instant B, that is, right after a reset write operation (when rearrangements resulting from the relaxation effect are still negligible), the resistance value of the phase-change material of such cells comprised therein reaches its minimum value, thus, currents that may pass through such cells at such fourth time instant B may reach higher values if compared with those that may pass through the same cells in moments after the fourth time instant B, for instance, in the third time instant A, as the resistance value of the phase-change material increases over time in response to the relaxation effect of the amorphous state of the phase-change material.
As previously described, read operations in single-ended PCM are performed using a reference current supplied, for instance, by a reference current generator, such reference current IREF being optionally:
Such read operations are performed, for instance, in response to a user request, after a given amount of time from a reset write operation, for instance, in the third time instant A, hence, the second current range RLA obtained in such third time instant A may be considered as one of the ranges used to define the reference current IREF for PCM architecture. The other of the ranges that may be used to define such reference current IREF may be the substantially constant first current range RHC,D.
However, it is noted that the first current distribution ISC,D of the first current range RHC,D may vary in response to set resistance drifts, such set resistance drift being dependent on temperature and time, that is, an increasing of the resistance, of the phase-change material of the cells within a PCM array.
Such set resistance drift that is may be a result of a change in the composition of the phase-change material in response to thermal atomic diffusion or collision against electrons at high temperatures, resulting in electromigration, leading to the movement of atoms of the phase-change material and resulting in a change in the composition of such phase-change material.
Such set resistance drift leads to a consequent lowering of the currents that passes through the cells comprised within a corresponding array, thus, the first current range RHC,D and the first current distribution ISC,D shift towards a fourth current range RHE and a corresponding fourth current distribution ISE respectively.
Therefore, to avoid failures of read operations after such set resistance drift, the other of the ranges used to define such reference current IREF may be the fourth current range RHE, obtaining the reference current IREF as illustrated in
However, as illustrated in
For instance, if a read operation is performed at the fourth time instant B, that is, right after such reset write operation, when rearrangements resulting from the relaxation effect are still negligible, to check the success of a reset write operation, the read operation, that in this case is referred to as reset verify operation, could fail, and therefore, the respective reset write operation will consequently be considered as failed, resulting in a high number of reset write attempts at increasing currents that may damage the cells after (many) writing cycles, that is, creating open bits that affect the durability of the PCM.
A possible solution may be obtained by performing reset verify operations, or any other similar read operation performed at the fourth time instant B or shortly thereafter, considering a second reference current HIREF, such second reference current HIREF having a higher value than that of the reference current IREF.
The use of the second reference current HIREF with a higher value than that of the reference current IREF may affect the reliability of read operations, as a set state, that is, a high logic value, of a group of cells may be mistaken with a reset state, that is, a low logic value, of the same group of cells since the resistance of the phase-change material of such cells when their state is a set state may be affected by the long-term drift phenomenon that results in a decreasing of the currents that may pass through such cells in the set state, moving the fourth current range RHE towards the higher reference current HIREF.
It is noted that both the wear of the PCM memory and high temperatures may increase such a long-term drift phenomenon affecting the cells in a set state.
It is noted that the first set of cells may be composed of any number of cells (any number smaller than the total number of bits of data to be written in the PCM memory) and that may be also the empty set, that is, if data to be written in the PCM memory is composed of bits all set to a high logic level.
Similarly, it is noted that the second set of cells may be composed of any number of cells (any number smaller than the total number of bits of data to be written in the PCM memory) and that may be also the empty set, that is, if data to be written in the PCM memory is composed of bits all set to a low logic level.
The method 10 is based on a balance between individual reset verify operations and loops of reset verify operations, considered respectively to minimize the impact of relaxation on the time of execution of write operations and improve the reliability of read operations to avoid a high number of reset write attempts at increasing currents, that is, current reset pulses, RP, that may damage a cell after many writing cycles, that is, generating “open bits”.
Therefore, the method 10 comprises—at least—the following operations:
After a failure of a set write operation, additional set write operations and set verify operations may be performed before determining a failure of the corresponding write operation.
Further set write operations, that is, set write operations following failed set write operations, may be performed with current set pulse of increased value.
It is noted that if each of the performed set write operations fails, for instance, a maximum number of performed set write operations fails, the method 10 may advantageously end (that is, the set write operations step 104 may be further configured to check if each of such maximum number of set write operations fails and, if that is the case, to proceed to an ending block 114) before performing other steps, for instance, reset verify operations 106 and 108.
After a failure of a reset write operation, additional reset write operations out of individual reset verify operations and/or loops of reset verify operations may be performed before determining a failure of the corresponding write operation.
In the exemplary embodiment shown in
Therefore, the method 10 may comprise considering 110 the write operation as successful and discontinuing set write verify operations and reset write verify operations in response to a first set write verify operation and a first reset write verify operation indicating that the cells in the first and in the second set are set to a low logic level or a high logic level respectively in response to the write operation.
The steps of the method 10 may be performed in a different order, for instance, by performing first a reset verify operation step 106, then a reset write operations step 102 followed by a set write operations step 104, and then again a reset verify operations steps 106 and/or 108, or other orderings.
The reset verify operations steps 106 and/or 108 may be performed a plurality of times as different steps of the method 10, for instance, the reset verify operations steps 106 may be performed both before the reset write operation step 102 and after the set write operations step 104.
It is noted that it may be advantageous to perform the set write operations step 104 after the reset write operations step 102 and before the reset verify operations steps 106 and/or 108 to benefit from the delay introduced by such set write operations between the reset write operations and reset verify operations, such delay being dependent on the time taken in performing the set write operations in such set write operations step 104, thus, facilitating the obtaining of a successful reset verify operation in such reset verify operations steps 106 and/or 108 since the resistance of the cells subject to such reset write operation in such reset write operations step 102 is increased in response to the relaxation phenomenon being partially run out.
It may be advantageous to perform a reset verify operations step 106 before a reset write operations step 102 so that if the cells to be set to a low logic level in such reset write operations step 102 are already set to such low logic level, the reset write operations step 102 may not be performed.
Similarly, it may be advantageous to perform (within the step referred to as 104) a set verify operation before set write operations so that if the cells to be set to a high logic level in such set write operations are already set to such high logic level, the set write operations may not be performed.
It may be advantageous to perform reset verify operations steps 106 (lasting for a time T1) comprising at least one individual reset verify operation before reset verify operations steps 108 (lasting for a time T2 which is higher than such time T1) comprising at least one loop of reset verify operations since a majority of the reset write operations will be concluded in response to performing, for instance, only a reset verify operations step 106 comprising one or more of the individual reset verify operations, thus, resulting in a reduction of the execution time needed for such reset write operations.
To summarize, the method 10 may comprise performing at least one individual reset write verify operation 106 prior to the looped reset write verify operations 108.
Other steps different from those reported in
Looped reset verify operations 108 may not be performed if a successful individual reset verify operation 106 has already been performed on same cells.
To summarize, in solutions disclosed herein, a method 10 of performing write operations in a Phase Change Memory, PCM device is disclosed. The PCM device comprising a first set of cells (that may be also an empty set) and a second set of cells (that may be also an empty set) configured to be set to a low logic level and to a high logic level, respectively, in response to a write operation comprising set write operations and/or reset write operations, wherein the method 10 comprises:
The method 10 starts in a start write operation block 100 configured to receive an indication comprising instructions for a write operation, that is, for the writing of data composed of a given number of bits in a memory location, and to send a start command SC to a first reset verify operation block 106a1.
The first reset verify operation block 106a1 is configured to receive the start command SC and, in response to its reception, it is further configured to perform a read operation, referred to as reset verify operation, on the cells of the memory location that contain bits that are to be set to a low logic level in the write operation and to provide the results R1 of such read operations to a first reset verify operation check block 106b1.
The first reset verify operation check block 106b1 is configured to receive the results R1 of the read operations and to check if all of the results R1 of the read operations are set to a low logic level.
If the check is successful, that is, if all of the results R1 of the read operations are set to a low logic level, the first reset verify operation check block 106b1 is configured to send a successful check signal Y to an end reset block 116a, otherwise, if the check is not successful, that is, if at least one of the results R1 of the read operations is set to a high logic level, the first reset verify operation check block 106b1 is configured to send an unsuccessful check signal N to a first reset write operation block 102a.
The end reset block 116a is configured to receive the successful check signal Y from the first reset verify operation check block 106b1 and, in response to its reception, it is further configured to set the value of an end reset variable ER, for instance, by writing its value in a specific memory location, in order to record that the reset verify operations on each of the cells of the memory location that contains a bit that is to be set to a low logic level are successful and to send an end signal ES1 to a set write operation block 104.
The first reset write operation block 102a is configured to receive the unsuccessful check signal N from the first reset verify operation check block 106b1 and, in response to its reception, it is further configured to perform a reset write operation on each of the cells of the memory location that contains a bit that is to be set to a low logic level in the write operation. Such reset write operations are performed using a first current reset pulse RP1 with a value of, for instance, 240 μA (microA): of course, that value is merely exemplary and non-limiting.
The reset write operation blocks 102 may be configured to perform reset write operations on each of the cells of the memory location that contains a bit that is to be set to a low logic level in the write operation and whose value is currently set to a high logic level.
The first reset write operation block 102a is further configured to send an end signal ES2 to the set write operation block 104 after performing the reset write operations.
The set write operation block 104 is configured to receive an end signal ES1, ES2 from the end reset block 116a or the first reset write operation block 102a and, in response to its reception, it is further configured to perform a set write operation on each of the cells of the memory location that contains a bit that is to be set to a high logic level in the write operation and to send an end signal ES3 to an end reset check block 116b.
Such set write operation block 104 may be configured to perform also set verify operations to check if the performed set write operations end successfully.
Set write operations and set verify operations can be performed in loops, for instance, the following operations may be performed:
A set verify operation with a corresponding set write operation may be repeated on such at least one cell for a given number of times until:
If the number of repetitions of set verify operations and set write operations reaches such given maximum number of repetitions, such set write operation block 104 may be further configured to set the value of a failure variable F, for instance, by writing its value in a specific memory location or sending an alert, for instance, to the microprocessor, the microcontroller, the logic circuit, or others, in order to record that the write operation of the respective cells is considered failed, and to send such failure variable F to an end write block 114 (described below).
The set write operation block 104 may be configured to perform set write operations on each of the cells of the memory location that contains a bit that is to be set to a high logic level in the write operation and whose value is currently set to a low logic level.
The end reset check block 116b is configured to receive the end signal ES3 and to check if the end reset variable ER is set, for instance, by reading its value in the specific memory location and comparing it with a desired reference value, for instance, a logic value set to a high logic level.
If the check is successful, that is, if the value of the end reset variable ER is equal to that of reference, the end reset check block 116b is configured to send a successful check signal Y to the end write block 114, otherwise, if the check is not successful, that is, if the value of the end reset variable ER is different from that of reference, the end reset check block 116b is configured to send an unsuccessful check signal N to a second reset verify operation block 106a2.
The end write block 114 is configured to receive a successful check signal Y or a failure signal F and to signal, for instance, to a microprocessor, a microcontroller, a logic circuit, or others, the conclusion of the write operation.
The end write block 114 may be configured to send an indication, for instance, to the microprocessor, the microcontroller, the logic circuit, or others, comprising the result of the write operation, for instance, fail/success, an indication of the cells with incorrect values in case of failure, or others.
The second reset verify operation block 106a2 is configured to receive the unsuccessful check signal N from the end reset check block 116b and, in response to its reception, it is further configured to perform a read operation, referred to as reset verify operation, on the cells of the memory location that contain bits that are to be set to a low logic level in the write operation and to provide the results R2 of such read operations to a second reset verify operation check block 106b2.
It is noted that such second reset verify operation block 106a2 can be configured to be performed after the set write operation block 104, that is, after set write operations and set verify operations that may also be looped as described above, to introduce a delay between the reset write operation performed by the first reset write operation block 102a and the subsequent reset verify operation performed by such reset verify operation block 106a2.
Therefore, such delay may depend on the time taken in performing the operations in the set write operation block 104, that is, the time taken by set write operations and set verify operations, facilitating the obtaining of a successful reset verify operation since the resistance of the cells subject to such reset write operation is increased in response to the relaxation phenomenon being partially run out.
The second reset verify operation check block 106b2 is configured to receive the results R2 of the read operations and to check if all of the results R2 of the read operations are set to a low logic level.
If the check is successful, that is, if all of the results R2 of the read operations are set to a low logic level, the second reset verify operation check block 106b2 is configured to send a successful check signal Y to the end write block 114, otherwise, if the check is not successful, that is, if at least one of the results R2 of the read operations is set to a high logic level, the second reset verify operation check block 106b2 is configured to send an unsuccessful check signal N to a second reset write operation block 102b.
The second reset write operation block 102b is configured to receive the unsuccessful check signal N from the second reset verify operation check block 106b2 and, in response to its reception, it is further configured to perform a reset write operation on each of the cells of the memory location that contains a bit that is to be set to a low logic level in the write operation. Such reset write operations are performed using a second current reset pulse RP2 with a value of, for instance, 270 μA (microA): of course, that value is again merely exemplary and non-limiting.
The value of the second current reset pulse RP2 may be higher than the value of the first current reset pulse RP1.
The second reset write operation block 102b is further configured to send an end signal ES4 to a first reset verify operation loop block 108a1 after performing the reset write operations.
The first reset verify operation loop block 108a1 is configured to receive the end signal ES4 and, in response to its reception, it is further configured to perform one or more read operations, for instance, from a single read operation to hundreds of read operations, referred to as reset verify operations, on the cells of the memory location that contain bits that are to be set to a low logic level in the write operation and to provide a verify success variable VS1 to a first reset verify operation loop check block 108b1.
Such verify success variable VS1 is set in order to record that at least one of the one or more reset verify operations is successful on each of the cells of the memory location that contains a bit that is to be set to a low logic level, that is, if at least one of the one or more reset verify operations verifies that all of the results of the read operations associated to such at least one reset verify operation are set to a low logic level.
In order to reduce the execution time of a write operation, the loop of reset verify operations may end when a first reset verify operation is successful, without performing the subsequent reset verify operations and setting the verify success variable VS1 thereafter.
It is noted that the loop performed in the first reset verify operation loop block 108a1 (and also in the following described reset verify operation loop blocks generally referred to with the reference 108a) may introduce additional delays between consecutive reset verify operations, for instance, if the duration of the delay introduced by the set write operation block 104 is not enough and additional time may be helpful.
The first reset verify operation loop check block 108b1 is configured to receive the verify success variable VS1 and to check if the verify success variable VS1 is set, for instance, by comparing its value with a desired reference value, for instance, a logic value set to a high logic level.
If the check is successful, that is, if the value of the verify success variable VS1 is equal to that of reference, the first reset verify operation loop check block 108b1 is configured to send a successful check signal Y to the end write block 114, otherwise, if the check is not successful, that is, if the value of the verify success variable VS1 is different from that of reference, the first reset verify operation loop check block 108b1 is configured to send an unsuccessful check signal N to a third reset write operation block 102c.
The third reset write operation block 102c is configured to receive the unsuccessful check signal N from the first reset verify operation loop check block 108b1 and, in response to its reception, it is further configured to perform a reset write operation on each of the cells of the memory location that contains a bit that is to be set to a low logic level in the write operation. Such reset write operations are performed using a third current reset pulse RP3 with a value of, for instance, 300 μA (microA): of course, that value is once more merely exemplary and non-limiting.
The value of the third current reset pulse RP3 may be higher than the value of the second current reset pulse RP2.
The value of the third current reset pulse RP3 may be higher than the value of the first current reset pulse RP1.
Therefore, the method 10 may comprise, in response to a reset write operation considered failed, repeating the reset write operations with a current reset pulse, for instance, RP2 or RP3, of increased value.
The third reset write operation block 102c is further configured to send an end signal ES5 to a second reset verify operation loop block 108a2 after performing the reset write operations.
The second reset verify operation loop block 108a2 is configured to receive the end signal ES5 and, in response to its reception, it is further configured to perform one or more read operations, for instance, from a single read operation to hundreds of read operations, referred to as reset verify operations, on the cells of the memory location that contain bits that are to be set to a low logic level in the write operation and to provide a verify success variable VS2 to a second reset verify operation loop check block 108b2.
Such verify success variable VS2 is set in order to record that at least one of the one or more reset verify operations is successful on each of the cells of the memory location that contains a bit that is to be set to a low logic level, that is, if at least one of the one or more reset verify operations verifies that all of the results of the read operations associated to such at least one reset verify operation are set to a low logic level.
The second reset verify operation loop check block 108b2 is configured to receive the verify success variable VS2 and to check if the verify success variable VS2 is set, for instance, by comparing its value with a desired reference value.
If the check is successful, that is, if the value of the verify success variable VS2 is equal to that of reference, the second reset verify operation loop check block 108b2 is configured to send a successful check signal Y to the end write block 114, otherwise, if the check is not successful, that is, if the value of the verify success variable VS2 is different from that of reference, the second reset verify operation loop check block 108b2 is configured to send an unsuccessful check signal N to an optional error correction block 112.
It is noted that if such error correction block 112 is not present, such unsuccessful check signal N is directly provided to a failure block 110.
The error correction block 112 is configured to receive the unsuccessful check signal N, to count the number of cells that are currently set to a wrong logic level, that is, the number of cells for which either a set write operation or a reset write operation fails, and to check if the number of the cells that are currently set to a wrong logic level is lower than or equal to the number of bits that may be corrected with an error detecting code, for instance, by parity bits, Error Correction Bits (ECC), Error Detection Bits (EDC), Cyclic Redundancy Check (CRC), or others.
If the checking step of the error correction block 112 is successful, that is, if the number of cells that are currently set to a wrong logic level is lower than or equal to the number of bits that may be corrected with an error detecting code, the error correction block 112 is configured to send a successful check signal Y to the end write block 114 and the corresponding write operation ends successfully.
Otherwise, if the checking step of the error correction block 112 is not successful, that is, if the number of the cells that are currently set to a wrong logic level is higher than the number of bits that may be corrected with an error detecting code, the error correction block 112 is configured to send an unsuccessful check signal N to a failure block 110.
It is noted that the number of the cells that are currently set to a wrong logic level is to be computed considering both the cells that are not correctly set to a high logic level in response to a set write operation and those that are not correctly set to a low logic level in response to a reset write operation.
Such method 10 may be configured to perform the operations of the error correction block 112 prior the setting of the value of the failure variable F by the set write operation block 104.
In such a case, if the number of repetitions of set verify operations and set write operations reaches the given maximum number of repetitions, the set write operation block 104 may be configured to perform the operations of the error correction block 112 prior the setting of the value of the failure variable F and:
Advantageously, to avoid a high number of reset write attempts at increasing currents that may damage the cell after (many) writing cycles, that is, creating open bits that affect the durability of the PCM, data written in the cells of the selected memory location may be considered as correct even if the reset verify operations, that is, both the individual reset verify operations and the loops of reset verify operations, fail but the error correction block 112 detects that number of cells that are currently set to a wrong logic level is lower than or equal to the number of bits that may be corrected with an error detecting code.
In order to prioritize the reliability of data written in the memory locations over the durability of the PCM, data written in the cells of the selected memory location may be considered as correct if both set verify operations and reset verify operations end successfully and the error correction block 112 detects that number of cells that are currently set to a wrong logic level is lower than or equal to the number of bits that may be corrected with an error detecting code.
The failure block 110 is configured to receive the unsuccessful check signal N from the error correction block 112, to set the value of a failure variable F, for instance, by writing its value in a specific memory location or sending an alert, for instance, to the microprocessor, the microcontroller, the logic circuit, or others, in order to record that the write operation of the respective cells is considered failed, and to send such failure variable F to the end write block 114.
As previously described, the blocks of the method 10 may be considered in a different order.
For instance, in a first exemplary embodiment the first reset write operation block 102a may be considered as the first block after the start write operation block 100, and the set write operation block 104, the first reset verify operation block 106a1, and the first reset verify operation check block 106b1 may be considered after such first reset write operation block 102a.
In the first exemplary embodiment provided, the end reset block 116a and the end reset check block 116b may be removed as the first reset write operation block 102a may provide its output, for instance, directly, to the second reset verify operation block 106a2 and the first reset verify operation check block 106b1 may provide the successful check signal Y to the end write block 114.
Therefore, some of the blocks illustrated in
It is noted that by using loops of reset verify operations on the one or more cells that are to be set to a low logic level instead of individual reset verify operations, the probability of having a second and/or a third current reset pulse RP2 and/or RP3 may be reduced by a high factor with respect to known solutions, for instance, in the structure disclosed in the exemplary embodiment shown in
The method generally referred to as 108a for performing reset verify reading attempts may be characterized with a maximum count variable MC and a time delay variable TD.
Such method 108a may be used to implement different reset verify operation loop blocks, for instance, both the first reset verify operation loop block 108a1 and the second reset verify operation loop block 108a2, by setting the values of the maximum count variables MC and the time delay variables TD for each block. It is noted that different reset verify operation loop blocks may have the same or different maximum count variables values MC and/or the same or different time delay variables values TD.
Therefore, the method 10 may comprise plural loops of looped reset write verify operations 108 with different upper count value MC for such looped reset write verify operations.
Similarly, the method 10 may comprise plural loops of looped reset write verify operations with different total time, that is, TD*MD, durations of such looped reset write verify operations. Therefore, the method 10 may comprise plural loops of looped reset write verify operations with different time delay values TD of such looped reset write verify operations.
The method 108a starts in a start reset verify loop block 200 configured to receive an end signal ES from any of the blocks previously described and to send a start instruction SI to a counter reset block 202.
The counter reset block 202 is configured to receive the start instruction SI and, in response to its reception, is further configured to reset the value of a counter to a known value, for instance, to zero, and to send an end counter reset signal ERC to a verify success reset block 204.
The verify success reset block 204 is configured to receive the end counter reset signal ERC and, in response to its reception, is further configured to reset the value of a verify success variable VS to a known value, for instance, to zero, and to send an end verify reset ERV signal to a maximum count check block 206.
It is noted that even the blocks of the method 108a may be considered in a different order, for instance, the counter reset block 202 and the verify success reset block 204 may be swapped.
The maximum count check block 206 is configured to receive the end verify reset ERV signal and/or an end count EC signal and, in response to its reception, is further configured to retrieve, for instance, from a variable, a memory location, a file, or others, the value of the respective maximum count variable MC and to check if the value of the counter, that is, the number of reset verify reading attempts performed, is equal to the value of such respective maximum count variable MC, that is, the maximum allowed reset verify reading attempts.
It is noted that if all the reset verify reading attempts up to the maximum allowed reset verify reading attempts fail, the reset verify operation loop is considered as failed.
If the check is successful, that is, if the value of the counter is equal to the value of such respective maximum count variable MC, the maximum count check block 206 is configured to send a successful check signal Y to an end reset verify loop block 218, otherwise, if the check is not successful, that is, if the value of the counter is different from the value of such respective maximum count variable MC, the maximum count check block 206 is configured to send an unsuccessful check signal N to reset verify read block 208.
The respective maximum count variable MC may be programmable and set, for instance, to 100.
It is noted that the method 108a performs a number of reset verify attempts comprised in a range from one to the value of the maximum count variable MC. If a successful reset verify attempt has not occurred in a number of attempts equal to the value of the maximum count variable MC, the method 108a ends and the reset verify operation loop is considered as failed.
To summarize, the method 10 may comprise:
The end reset verify loop block 218 is configured to receive a successful check signal Y and/or a verify success variable VS and to provide the verify success variable VS as output.
If the verify success variable VS is not received by the end reset verify loop block 218, such block 218 may be configured to provide as output a verify success variable VS set to a default value, for instance, to zero.
If the verify success variable VS is not received by the end reset verify loop block 218, such block 218 may be configured to provide as output a verify success variable VS retrieved, for instance, from a variable, a memory location, a file, or others, wherein such verify success variable VS is stored.
If the value of the verify success variable VS provided as output is equal to the reset value associated with such verify success variable VS, the plurality of reset verify reading attempts, that is, the reset verify operation loop, is considered as failed, otherwise, the reset verify operation loop is considered successful.
The reset verify read block 208 is configured to receive the unsuccessful check signal N from the maximum count check block 206 and, in response to its reception, it is further configured to perform a read operation, referred to as reset verify operation, on the cells of the memory location that contain bits that are to be set to a low logic level in the write operation and to provide the results R of such read operations to a reset verify check block 210.
The reset verify check block 210 is configured to receive the results R of the read operations and to check if all of the results R of the read operations are set to a low logic level.
If the check is successful, that is, if all of the results R of the read operations are set to a low logic level, the reset verify check block 210 is configured to send a successful check signal Y to a verify success set block 216, otherwise, if the check is not successful, that is, if at least one of the results R of the read operations is set to a high logic level, the reset verify check block 210 is configured to send an unsuccessful check signal N to a delay block 212.
The verify success set block 216 is configured to receive the successful check signal Y from the reset verify check block 210 and, in response to its reception, is further configured to set the value of the verify success variable VS to a value different from that of reset, for instance, to a high logic level, that is, “1”, indicating the success of the reset verify operation loop and to send such verify success variable VS to the end reset verify loop block 218.
The delay block 212 is configured to receive the unsuccessful check signal N from the reset verify check block 210 and, in response to its reception, is further configured to retrieve, for instance, from a variable, a memory location, a file, or others, the value of the respective time delay variable TD, that is, indicating a time delay between subsequent reset verify operation attempts, and to wait for the amount of time indicated in such time delay variable TD.
The respective time delay variable TD may be programmable and set, for instance, to 1 μs.
It is noted that such time delay variable TD may be set in order to decrease the effects of the relaxation phenomenon, as after such time delay variable TD the relaxation phenomenon may be partially run out.
As previously noted, the method 108a performs a number of reset verify attempts comprised in a range from one to the value of the maximum count variable MC, therefore, if a delay equal to the time delay TD is introduced among two reset verify attempts, the maximum execution time of the reset verify operation loop is about MC*TD, for instance, if MC=100 and TD=1 μs, the maximum execution time is about 100 μs.
Therefore, if all the reset verify reading attempts within a time window equal to about MC*TD fail, the reset verify operation loop can be considered as failed.
To summarize, a method 10 as described herein may comprise:
An optimal value for such time delay variable TD may be obtained empirically.
It is noted that reset verify attempts performed after a given reset verify attempt have a reduced failure probability since the probability to fail a reset verify operation, that is, a read operation following a write operation, decrease over time according to the relaxation phenomenon.
Therefore, the time delay TD may be selected by considering a desired balance between the maximum execution time of the reset verify operation loop and the probability to fail a reset verify operation, for instance, obtained by empirically testing the decreasing of the failure probability over time according to the relaxation phenomenon.
The delay block 212 is further configured to provide an end delay ED signal indicating the end of the waiting to a counter block 214.
The counter block 214 is configured to receive the end delay ED signal and, in response to its reception, is further configured to add, for instance, a unitary value, to the value of the counter and to send the end count EC signal to the maximum count check block 206.
The methods 10 and 108a described here can be implemented using one or more computer products loadable in a memory of at least a computer and comprising portions of software code for executing the previously described phases.
Solutions as described herein facilitate achieving a method for reducing the failure probability of reset verify operations using a balance between individual reset verify operations and loops of reset verify operations, considered respectively to minimize the impact of relaxation on write operations time and improve the reliability of read operations to avoid a high number of reset write attempts at increasing currents that may damage the cell after many writing cycles.
Thus, solutions as described herein facilitate achieving single-ended PCM architectures that minimize, that is, reduce or substantially remove, the impact of the resistance drift of a phase-change material, reducing production costs and the required area of PCM architectures without sacrificing their durability.
In addition, solutions as described herein facilitate achieving a desired balance between reliability and time of execution by balancing the number of individual reset verify operations and loops of reset verify operations, wherein such loops of reset verify operations may additionally reduce the probability of having a second and/or a third current reset pulse, increasing the durability of the PCM and avoiding open bits.
Without prejudice to the underlying principles, the details and the embodiments may vary, even significantly, with respect to what has been described by way of example only without departing from the scope of the embodiments.
The extent of protection is determined by the annexed claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 102023000019332 | Sep 2023 | IT | national |
