Method of producing silicon and similar wafers buffered for the deposition of metal oxide superconducting (MOS) polymer composites and the like by insulating metal oxides (IMO) suitable as substrates for MOS, and novel buffered wafers provided thereby

Abstract

New Method of buffering silicon and similar semiconductor wafers with appropriate metal oxide layers which, in turn, have been found to be excellent substrates for MOS depositions without interaction with the semiconductor surface, and novel buffered wafers produced thereby.

Description

With the constant demands for higher density of circuitry in VLIC applications, the use of superconducting VLIC devices appears to be an ultimate answer. This requires depositing metal oxide superconductor (MOS) patterns on Si wafers (or GaAs or other semiconductor wafers and the like).

In said copending U.S. Pat. application Ser. No. 266,014, there is disclosed such a process to form integrated circuits on a silicon semiconductor or other suitable substrate in which circuit components can be formed that comprises applying to a major surface of the substrate, as a thin-layer composite, a resist in the form of a polymer-metal-complex (PMC) precursor which includes materials that can be made superconducting (MOS) and at least one thermally stable heteratom resist polymer (HRP) intermixed. The thin-layer composite is irradiated to achieve selective removal of portions of the thin-layer composite, whereby many electrical devices can be formed in the substrate; and then the polymer-metal-complex (PMC) precursor is oxidatively processed to convert the precursor to a metal-oxide-superconductor (MOS) to carry electric current between said devices The heteroatom resist polymer (HRP) may comprise a large number of successive aromatic rings with intervening structures that destroy the colinear character and coplanar character typical of the successive aromatic rings to render the heteroatom (HRP) sensitive to and unstable in the presence of radiation used to create integrated electrical circuits, yet stable at temperatures used to create integrated circuits and stable in common organic solvents; and it may comprise a copolymer containing both partially and completely condensed structure units taken from the group consisting essentially of amic acid, imide, imidazole, oxadiazole, triazole and oxazole and their precursor groups. The heteroatom resist polymer (HRP) may also be a synthetic polymer taken from the group consisting of negatively-charged carboxylate and solfonate, or a synthetic polymer taken from a group of polymers having polar groups of amide, ester, hydroxy, ether and sulfide. The polymer-metal-complex (PMC) may include metals taken from the group consisting of Y, Ba, Bi, Sr, Ca, Tl, Pb, Ag and Cu.

While initial experiments have proved most encouraging with this technique, as described, for example, in my articles "Polymer Precursor Synthesis of High T.sub.c Superconductors", Polymer Bulletin 21, 1-4 (1989) and "Polymer Precursor Synthesis and Characterization of YBa.sub.2, Cu.sub.3, O.sub.7-x ", Physical Review B, Vol. 38, No. 6, 1 Dec. 1988, pp. 11853-6, in some of the more stringent uses of applications of MOS deposition on Si wafers and the like, particularly with other techniques than above discussed, several difficulties may arise. Specifically, it has been found that the silicon is highly reactive with the metal ions of MOS, forming metal silicides. These reactions have been found to occur even for Si wafers having their surfaces oxidized to SiO.sub.2 in view of the fact that Si atoms have high diffusivity in SiO.sub.2. On the other hand, thin films of MOS have been successfully deposited on certain insulating metal oxides (IMO) substrates, such as LaAlO.sub.3, LaGao.sub.3, ZrO.sub.2, SrTiO.sub.3, MgO, and have been shown to exhibit >10.sup.6 A cm.sup.-2 current density as described in said copending application and articles.

It has now been discovered that, using the polymer-metal-complex (PMC) precursor technique of said articles and copending application, metal oxide-buffered Si and related semiconductor wafers can be made which serve admirably as substrates for depositing single and multilayer MOS patterns.

An object of the present invention, accordingly, is to provide a new method of buffering silicon and similar semiconductor wafers with appropriate IMO layers which, in turn, have been found to be excellent substrates for MOS depositions without interaction with the semiconductor surface, and novel buffered wafers produced thereby.

Other and further objects will be explained hereinafter and are more particularly delineated in the appended claims.

In summary, from one of its aspects, the invention embraces a method of buffering semiconductor wafers from interaction with metal oxide superconducting (MOS) materials to be deposited upon a surface thereof, that comprises, applying to the semiconductor wafer surface a coating of polymer-metal-complex (PMC) to form thereon a corresponding IMO, preferably 0.1 to 10 .mu.m thickness, thin layer adhered to the said wafer surface and non-reactive therewith, said layer being adapted to receive MOS deposition thereupon and buffering the same from reaction with the wafer surface. Preferred and best mode embodiments are hereinafter described.

Ten grams of Mg(NO.sub.3).sub.2 6H.sub.2 O and 20 g of copolymer of vinylacetate and methacrylic acid was dissolved in 100 g of dimethyl formamide (DMF) spin coating the PMC solution on a silicon wafer at 4000 rph for 1 minute. About 1.4 .mu.m thick film of PMC precursor was thereby obtained. It was heated under an air atmosphere from room temperature to 700.degree. C. in 2 hours and then maintained at 700.degree. C. for 0.5 hour. A very smooth MgO insulating buffer layer 0.2 .mu.m thin was obtained, well-adhered to and non-reactive with the silicon surface and providing an excellent substrate for MOS deposition thereon without interaction with the silicon surface.

I have also successfully prepared buffered Si wafers of other insulating-type metal oxides known to be good substrates for MOS by this same process using other functional copolymers such as polyamic acid. These examples are given in Table I below. The buffered wafers are free of pinholes and can readily be used to prepare superconductive VLIC structures as explained above.

TABLE I______________________________________Preparations of buffered Si wafersComposition of Precursors Co-Buffer Compound polymer DMF HNO.sub.3______________________________________MgO Mg(NO.sub.3).sub.2.6H.sub.2 O 10 g 20 g 100 g 0 gLaGaO.sub.3 La(NO.sub.3).sub.2 6H.sub.2 O 1.732 g 4.2 g 50 g 1.0 g Ga(NO.sub.3).sub.3 1.023 gSrTiO.sub.3 Sr(NO.sub.3).sub.2 2.12 g 5.0 g 60 g 1.0 g (C.sub.5 H.sub.5).sub.2 TiCl.sub.2 2.49 gNdGaO.sub.3 Nd(NO.sub.3).sub.3 5H.sub.2 O 0.408 g 1.4 g 20 g 1.0 g Ga(NO.sub.3).sub.3 2.255 gGdGa Gd(NO.sub.3).sub.3.5H.sub.2 O 0.451 g 1.4 g 20 g 1.0 g Ga(NO.sub.3).sub.3 2.255 gYSZ Y(NO.sub.3).5H.sub.2 O 0.628 g 7.8 g 50 g 1.0 g Zirconium 4.09 g acetylaceonateLaAlO.sub.3 La(NO.sub.3).sub.3.6H.sub.2 O 4.33 g 16.0 g 80 g 1.0 g Al(NO).sub. 3.9H.sub.2 O 3.75 g______________________________________

Further modifications will occur to those skilled in the art and such are considered to fail within the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor wafer suitable for MOS deposition upon a surface thereof comprising a thin insulating metal oxide buffer layer adhered to said surface and compatible with MOS materials deposited thereon.

2. A coated/buffered semiconductor wafer as claimed in claim 1 and in which said metal oxide buffer layer was formed from a PMC precursor and is of the order of microns in thickness.

3. A coated/buffered semiconductor wafer as claimed in claim 2 and in which the buffer layer insulating metal oxide is selected from the group consisting of MgO, LaGaO.sub.3, SrTiO.sub.3, NdGaO.sub.3, GdGa, YSZ and LaAlO.sub.3, and the semiconductor is one of Si and GaAs.

4. A method of buffering semiconductor wafers from undesirable chemical interaction with metal oxide superconducting (MOS) materials to be deposited upon a surface thereof, that comprises, applying to the semiconductor wafer surface a coating of polymer-metal-complex (PMC) to form thereon a corresponding insulating metal oxide thin layer adhered to the said wafer surface and non-reactive therewith, said layer to receive MOS deposition thereupon and buffering the same from reaction with the wafer surface.

5. A method as claimed in claim 4 and in which the semiconductor is silicon and the insulating metal oxide buffer layer is selected from the group consisting of MgO, LaGaO.sub.3, SrTiO.sub.3, NdGaO.sub.3, GdGa, YSZ and LaAlO.sub.3.

6. A method as claimed in claim 5 and in which said metal oxide buffer layer is formed in the micron thickness range.

7. A method as claimed in claim 6 and in which said thickness is in the range of 0.1 to 10 .mu.m.

8. A semiconductor wafer formed by the process of claim 4.

9. A method as claimed in claim 1 and in which the (MOS) material is prepared from a polymer-metal-complex (PMC) precursor including metals selected from the group consisting of Y, Ba, Bi, Sr, Ca, Ti, Pb, Ag and Cu intermixed with a thermally stable heteroatom resist polymer comprising successive aromatic rings with intervening structures that render the same sensitive to and unstable in the presence of radiation and selected from the group consisting of amic acid, imide, imidazole, oxadiazole, triazole and oxazole and their respective precursors, with the said material converted by oxidation to (MOS) characteristics following irradiation of the same to create the desired (MOS) conductor pattern.