Method of programming a memory cell to contain multiple values

Abstract

A method for programming multiple values in an individual flash memory cell is disclosed. An individual flash cell is programmed by holding the bit line, corresponding to the particular memory cell to a value, V.sub.d, while the voltage on the control gate, V.sub.g, of the memory cell is varied. By varying the voltage on the control gate, multiple values are stored in the memory cell. The resulting values are self-convergent, therefore, verify circuitry becomes unnecessary.

Description

FIELD OF THE INVENTION

This invention relates to flash memory cells, and more particularly, to an improved method of programming flash EEPROM memory cells.

BACKGROUND OF THE INVENTION

There is a class of non-volatile memory devices known as flash electrically erasable and programmable read only memory devices (EEPROM). The term "flash" refers to the EEPROMs having data written to or programmed, by a process known as hot electron injection and being erased by Fowler-Nordheim (FN) tunnelling.

Flash EEPROM memory cells may be formed on a semiconductor substrate having diffused therein a n+drain region, a n-type source region and a channel region positioned between the drain and source regions. A tunnel oxide is formed on the silicon substrate separating a floating gate from the source and drain regions. A control gate is separated from the floating gate by another insulating layer.

According to conventional operation, flash memory cells are programmed by inducing hot electron injection of electrons from the channel region near the drain region to the floating gate. Electron injection will carry a negative charge onto the floating gate. This injection mechanism is normally induced by grounding the source region, applying a relatively high positive voltage (approximately 12V) to the control gate and applying a moderate voltage (approximately 5V) to the drain region in order to generate high energy (hot) electrons.

Erasing flash EEPROM memory cells is typically carried out by Fowler-Nordheim tunnelling between the floating gate and the source (known as source erase or negative gate erase) or between the floating gate and the substrate (known as channel erase).

A drawback associated with conventional flash memory cells is that, in an array of flash EEPROM memory cells, the write operation is performed one byte at a time while erasing of the memory cells is performed in a sector by sector fashion within the array. For example, in order to change one byte of data, each cell in the memory array has to be first programmed (or "charged"), representing a "0" value, then erased (or "discharged"), representing a "1" value, and finally the new byte of data is written to the particular location, with the memory cells whose contents that have not been changed being re-written to their previous values.

Another drawback associated with conventional flash memory devices is that a particular flash cell can only store one bit of information, either a "1" or "0". In the programmed state, also known as "charging", the floating gate of a memory cell contains a net negative charge due to the presence of electrons injected from the drain area. For n-channel devices, when the cell is in the programmed state, the electrons on the floating gate keep the n-channel transistor in the logical off "0" state. In the erased state, also known as "discharging," there are no electrons present on the floating gate. When the memory cell is erased, the N-channel transistor is in the logical on "1" state.

Attempts have been undertaken to store multiple values within a single flash memory cell. One such approach is to divide the flash cell into four segments, or layers. A first voltage is applied to divide the flash cell into two high and then, two lower layers. A second voltage is then applied to more accurately place a bit of data into one of the four layers. A verification step is then performed to ensure the accuracy of bit placement. These steps are repeated each time a bit of data needs to be stored in a particular segment of the memory cell.

A drawback associated with such a programming method is that verify circuitry is needed to check whether a particular cell has been properly programmed after each respective bit of data has been placed in a particular flash cell segment. The verify circuitry needed for this operation takes up valuable space on the semiconductor die. Moreover, a substantial portion of the time needed to program a particular memory cell is taken up by the operation of the verify circuitry.

A consequential drawback associated with conventional programming methods is the speed with which data is written to the memory cells. For example, charging one byte of memory through conventional programming methods requires 3 .mu.sec. The time required for discharging the same one byte of memory (the time needed for electrons on the floating gate to tunnel through the gate oxide) is 0.5 sec. With a memory array having 64K bytes (512K bits), between 700 msec-900 msec is required to change as little as one byte of memory. This process must be performed each time an individual byte of memory has to be changed.

As the trend to fabricate memory devices having high density continues, the ability of individual memory cells of an array to store multiple bits of information and to be able to change the data stored within a particular memory cell without reprogramming the entire array becomes of increasing importance to designers and manufacturers alike.

SUMMARY OF THE INVENTION

The present invention solves the aforementioned and related problems associated with conventional flash memory devices and the methods of programming the same. In the preferred method of the present invention, a flash memory cell is programmed to contain multiple bits of information by applying a first voltage, V.sub.d, to the drain of the memory cell; applying a plurality of non-zero voltages, V.sub.g, to the respective gate of the memory cell; and by floating the source of the memory cell with the substrate being held at ground potential. Also, according to the preferred method of the present invention, the programming of an entire page of memory is accomplished by applying a first voltage, V.sub.d, to a selected bit line of a page; applying a second voltage, V.sub.g, to each wordline along the selected bit line while floating the sources of the memory cells along the selected bit line and grounding the substrate.

An advantage of the present invention is that less physical space is needed on a chip for manufacturing a memory array because verify circuitry is not needed.

Another advantage of the present invention is that the memory cell programming time is reduced in that it is no longer necessary to verify the content of the memory cell after programming.

A further advantage of the present invention is the ability to program individual memory cells to store more than one value; hence, improving memory density.

A feature of the present invention is that the layout of the memory cell and the fabrication process for producing the memory cell can be performed in a conventional manner.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other advantages and features of the present invention will become apparent from the following description of the preferred embodiments, taken in conjunction with the accompanying drawings, where like numerals represent like elements, in which:

FIG. 1 illustrates a memory cell structure according to the present invention.

FIG. 2 is a chart showing the convergent characteristics of threshold voltages according to the method of present invention.

FIG. 3 is a schematic diagram representing an architecture for performing page mode programming of a memory array according to the method of the present invention.

DETAILED DESCRIPTION

The present invention provides an improved method of programming a flash EEPROM memory cell to contain multiple bits of information. The present invention comprises a programming method where individual cells of a memory array can be programmed to contain multiple bits of information as opposed to conventional programming methods where a particular cell only holds one bit of information.

FIG. 1 illustrates a poly-II type metal oxide field effect transistor memory cell according to the present invention. The memory cell is fabricated on a P-type semiconductor substrate 100, having diffused therein a drain region 102 heavily doped with arsenic and a heavily doped n+ source region 104. A tunnel oxide region 105, separates the heavily doped source and drain regions 102, 104, respectively from a floating gate 107. A control gate 106 is separated from the floating gate 107 by an insulating layer 109. Although the present description is directed to a device fabricated on a p-type semiconductor substrate, it would be readily apparent to one of ordinary skilled in the art that an n-type semiconductor material can be used to fabricate the substrate. Further, impurities other than arsenic may be used to dope the source and drain regions of the MOSFET 10.

As discussed above, flash memory cells are conventionally programmed by applying a particular voltage, V.sub.g, to the control gate 106 of the MOSFET 10 while at the same time applying a particular voltage, V.sub.d, to the drain region 102 of MOSFET 10 while floating the source region 104 and grounding the substrate 100. By applying a particular voltage to the source and drain regions of the memory cell, electrons or holes from the channel region 112 near the drain region 102 are injected onto the floating gate 107, thereby changing the threshold voltage (V.sub.t) of the memory cell 10. The threshold voltage, V.sub.t, represents the stored value of the memory cell. Electron (negative charge) injection onto the floating gate from the substrate will increase V.sub.t. Hole (positive charge) injection onto the floating gate will decrease V.sub.t. A thorough recitation of the principles and effects of electron and hole movement can be found in Tang, et al. Differentiating Impacts of Hole Trapping vs. Interface States on TDDB Reduction in Thin Oxide Gated Diode Structures, IEEE/IRPS 1993 and is incorporated herein. FIG. 2 illustrates this relationship in more detail.

FIG. 2 shows a plot of drain current, I.sub.d, and floating gate current, .vertline.I.sub.g .vertline., versus floating gate potential, V.sub.fg, for the memory cell 10 with fixed values of drain voltages, V.sub.d. Line A represents V.sub.d =8V; Line B represents V.sub.d =9V; and Line C represents V.sub.d =10V with the substrate at ground potential and the source floating. As shown in FIG. 2, for a fixed drain voltage V.sub.d =7V, represented by Line D, the drain junction is not in the breakdown region, with a measured drain current, I.sub.d, below 1 .mu.A and a gate current, I.sub.g, below 1 pA.

When a fixed voltage, V.sub.d =8V, (Line A) is applied to the drain 102 of the memory cell 10, the threshold voltage, V.sub.t, of the memory cell 10 converges to a value of about 2.5V. When the floating gate potential is greater than about 2.5V, electron injection will occur, (I.sub.g <0), and the injected electrons will lower the floating gate potential, V.sub.fg, to approach the convergent voltage, V.sub.cvg, of 2.5V. When V.sub.fg is less than about 2.5V, hole injection occurs which increases V.sub.fg to approach the convergent voltage, V.sub.cvg, of about 2.5V. Therefore, carrier injection will always converge V.sub.fg to about 2.5V when V.sub.d =8.sub.v it is applied to the drain region with the source floating.

For the memory cell illustrated in FIG. 1, when the substrate is grounded, the voltage present on the floating gate can be written as:

V.sub.fg =GC.multidot.V.sub.g +SC.multidot.V.sub.s +DC.multidot.V.sub.d +Q/C.sub.total (1) which represents the floating gate potential (voltage), V.sub.fg, as a function of the charge present on the control gate as well as the charge present on the source terminal and drain terminal. In equation (1), GC represents gate coupling and has the value of C.sub.1 /C.sub.total ; SC represents source coupling, having a value of C.sub.2 /C.sub.total ; DC represents drain coupling, having a value of C.sub.3 /C.sub.total ; C.sub.1 represents the capacitance between the floating gate and the control gate; C.sub.2 represents the capacitance between the floating gate and the source; and C.sub.3 represents the capacitance between the floating gate and the drain. V.sub.g, V.sub.s, and V.sub.d represents the applied voltages on the control gate, source and drain, respetively; Q represents the charge on the floating gate, and C.sub.total represents a total capacitance of the memory cell, defined as C.sub.1 +C.sub.2 +C.sub.3.

When the memory cell is initially erased, Q=0. The cell is then turned on when UV.sub.-- V.sub.t (a constant value) is applied to the control gate and the floating gate 107 voltage is V.sub.fg =UV.sub.-- V.sub.t .multidot.GC. When there is a charge, Q, already on the floating gate 107, in order to turn on the memory cell, a voltage V.sub.t has to be applied to the control gate 106, so the voltage on the floating gate 107 is represented by ##EQU1## thus, ##EQU2## can be represented by:

Q/C.sub.total =-(V.sub.t -UV.sub.-- V.sub.t).multidot.GC (2) Substituting equation 2 into equation 1, yields: V.sub.fg =GC.multidot.V.sub.g +DC.multidot.V.sub.d -(V.sub.t (t0)-UV.sub.-- V.sub.t).multidot.GC (3)

Thus, for a flash cell with an initial threshold voltage V.sub.t (t0), V.sub.t at time t0, the voltage present on the floating gate during programming can be written as shown above in equation 3. Whether electrons or holes will be introduced onto the floating gate depends upon whether the voltage present on the floating gate, V.sub.fg is larger or smaller than the convergent voltage, V.sub.cvg, as shown in FIG. 2.

At a subsequent time, t1>t0, the voltage on the floating gate reaches the convergence voltage, V.sub.cvg, due to charge accumulation by either electron or hole injection, as described by equation 4 below:

V.sub.fg =GC.multidot.V.sub.g +DC.multidot.V.sub.d -(V.sub.t (t1)-UV.sub.-- V.sub.t).multidot.GC=V.sub.cvg (4)

Since a convergent voltage, V.sub.cvg, is known for the memory cell shown in FIG. 1, the applied voltage at the control gate, V.sub.g, can be obtained as a function of the desired threshold voltage, V.sub.t (t1) from equation (4):

GC.multidot.V.sub.g =V.sub.cvg -DC.multidot.V.sub.d +(V.sub.t (t1)-UV.sub.-- V.sub.t).multidot.GC (5)

Equation (5) indicates that for any desired threshold value (representing one bit of information), V.sub.t, at convergent time t1, i.e., V.sub.t (t1), there is a corresponding unique control gate voltage, V.sub.g. Thus, after a period of time (t1-t0) of applying a voltage, V.sub.g, to the control gate 106, the threshold voltage, V.sub.t, of the memory cell 10 will change to V.sub.t (t1) regardless of the threshold voltage, V.sub.t, present on the floating gate at time t0.

Accordingly, as shown above with respect to equations 1-5 and illustrated in FIG. 2, a flash memory cell may be programmed to store a set of different values of V.sub.t by applying a particular fixed voltage, V.sub.d, to the drain of the memory cell and by applying a set of different voltages, V.sub.g, each corresponding to the value to be stored, to the gate of the memory cell. Each voltage, V.sub.g, applied to the gate of the memory cell corresponds to a particular threshold voltage, V.sub.t, and hence a particular value of data stored in the cell. In one method of the present invention, four values (2 bits) can be stored in each memory cell. However, in an alternative embodiment, storage of more than two bits (i.e., 4, 8, 16, etc.) is possible by using the method of the present invention. The resulting threshold voltages are self-convergent; thus, verify circuitry is not needed. Because verify circuitry is not necessary, the time used to verify that the memory cell has been programmed is also not necessary; thereby, greatly reducing programming time. Also, because verify circuitry is not needed, valuable space is made available for the introduction of more memory cells, or to permit the further reduction of the area taken up by the memory cells.

FIG. 3 illustrates a memory array structure used in performing page mode programming according to one method of the present invention. FIG. 3 shows a memory array 40 containing 512 wordlines (WL.sub.0 -WL.sub.511) and 512 registers (Register .sub.-- 0-Register .sub.-- 511). Each register contains one byte (eight bits) of information, with 512 bytes constituting one page of memory. In one embodiment of the method of the present invention, the contents of the memory array are altered one bit line at a time.

According to one embodiment of the present invention, in order to program 512 memory cells on the same bit line, i.e., (BL.sub.0), the bit line (BL.sub.0) is selected by applying a fixed voltage (8V) to the bit line. The unselected bit lines (BL.sub.1 -BL.sub.511) are kept at ground potential. The values to be programmed into each memory cell on the selected bit line (BL.sub.0) is determined by the corresponding value stored in the first two bits (D0, D1) of the respective register. There are four possible combinations (00, 01, 10, 11) for the values of D0 and D1. Thus, each combination results in a specific voltage (V.sub.g) being applied to all the wordlines. For example, the values to be written to the memory cells along BL.sub.0 are stored in the first two digits (D0, D1) of the corresponding Register.

As discussed above, by using the method of the present invention, a memory cell can store two binary values based upon the voltage, V.sub.g, applied to the control gate 408 via WL.sub.0. Because each memory cell can be programmed to have four values, two binary digits are needed to represent the four values. Particularly, for the first memory cell 400 along BL.sub.0, the voltage, V.sub.g, to be applied to the gate 408 along WL.sub.0 is determined by the values of D0 and D1 stored in Register.sub.-- 0. In Register.sub.-- 0, D2 and D3 are used to determine the voltage applied to WL.sub.0 when BL.sub.1 is selected. Likewise, D4 and D5, in Register .sub.-- 0, are used to determine the voltage applied to WL.sub.0 when BL.sub.2 is selected. Also, D6 and D7, in Register.sub.-- 0, are used to determine the voltage applied to WL.sub.0 when BL.sub.3 is selected. As such, one (1) byte of information in a register can be programmed into four cells in the memory array 40. For comparison, eight cells are required to store the same one byte of information using conventional programming methods.

During programming, the V.sub.g determined by the corresponding two digits in each corresponding register within buffer 500 is applied to each wordline simultaneously so that for any selected bitline, any control gate has a predetermined voltage applied to it thereby simultaneously programming the memory cells along a single bitline. This method can be used to write data to memory locations for every four bitlines, BL.sub.4 -BL.sub.7, BL.sub.8 -BL.sub.15, etc.

The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, modification and variation of the invention are possible in light of the above teaching. A method of programing a memory cell to have multiple values was chosen and described in order to best explain the principals of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims

1. A method of programming a cell having a drain, a control gate, and a source positioned on a substrate with multiple data values, comprising the steps of:

applying a voltage, v.sub.d, to said drain during the programming of a predetermined first data value of said cell;

applying a predetermined voltage, v.sub.g, to said control gate of said cell, responsive to said predetermined first data value, during the programming of said cell;

holding said substrate at ground potential; and

floating said source.

2. The method of claim 1, wherein said voltage v.sub.d, has the value of approximately 8v.

3. The method of claim 1, wherein said voltage v.sub.g, has a value in the range of approximately 8v to approximately 10v.

4. In a flash memory cell having a source, a control gate coupled to a respective word line and a drain coupled to a respective bit line, a method of programming said flash memory cell comprising the steps of:

applying a first voltage v.sub.d, to said respective bit line during the programming of a predetermined first data value;

applying a second voltage, v.sub.g, to said respective word line, responsive to said predetermined first data value, during the programming of said cell;

floating said source;

applying a third voltage, v.sub.g, to said respective word line, responsive to a predetermined second data value; and

holding a substrate at ground potential.

5. The method of claim 4, wherein said voltage v.sub.d has the value of approximately 8v.

6. The method of claim 4, wherein said voltage v.sub.g has a plurality of values.

7. The method of claim 6, wherein said voltage v.sub.g has a value in the range of approximately 8v to approximately 10v.

8. In an array of memory cells formed on a substrate, a plurality of memory cells having a source, a drain and a gate, wherein a plurality of bit lines are connected to said respective plurality of drains, and wherein a plurality of word lines are connected to said respective plurality of gates, comprising the steps of:

applying a voltage, v.sub.d, to a first bit line in said plurality of bit lines;

applying simultaneously a respective plurality of voltages, v.sub.g, to said plurality of word lines, responsive to a respective plurality of data values;

floating said respective sources; and

holding said substrate at ground potential.