Claims
- 1. A method of electrically coupling a central processing unit (CPU) of a server to a plurality of interface modules comprising:
routing an I/O bus having a first format from said central processing unit to primary sides of a plurality of bus adapter chips; and routing an I/O bus of said first format from secondary sides of said bus adapter chips to respective ones of said interface modules.
- 2. The method of claim 1, wherein the bus adapter chips comprise electrical hardware which provides arbitered access along the I/O busses.
- 3. The method of claim 1, wherein routing the I/O buses to and from bus adapter chips comprising electrically isolating the CPU from electrical disruption when one of the interface modules is removed.
- 4. The method of claim 1, further including mounting a plurality of interface cards in interface card slots in said plurality of interface modules.
- 5. The method of claim 1, further including removably mounting said interface modules on a chassis.
- 6. The method of claim 5, wherein removably mounting the interface module comprises mounting said interface module such that said interface module may be removed from said chassis and disconnected electrically from said CPU or mounted on said chassis and connected electrically to said CPU without powering down said CPU.
- 7. A method of electrically coupling a plurality of interface modules to a CPU such that at least one of the interface modules can be disconnected without powering down the remaining interface modules or the CPU, said method comprising:
mounting a CPU on a chassis; removably mounting a plurality of interface modules to said chassis; mounting a backplane printed circuit board on the chassis, wherein the backplane printed circuit board comprises at least one bus adapter chip for each of the plurality of interface modules, and wherein each bus adapter chip has a primary side and a secondary side, and wherein each bus adapter chip has electrical hardware that isolates the primary side from the secondary side when the corresponding interface module has been removed from the chassis; routing an I/O bus on said backplane printed circuit board from the primary side of the at least one bus adapter chip to the CPU; and routing an I/O bus on said backplane printed circuit board from the secondary side of the at least one bus adapter chip to the corresponding one of the interface modules.
- 8. The method of claim 7, wherein the at least one bus adapter chip comprises electrical hardware providing arbitered access and speed matching along the I/O busses.
- 9. The method of claim 7, wherein the I/O busses comprise peripheral component interconnect (PCI) busses.
- 10. The method of claim 9, wherein said act of mounting the plurality of interface modules to the backplane printed circuit board comprises the acts of:
connecting a 180 pin female connector on said backplane printed circuit board with a 180 pin male connector on a interface module of said plurality of interface modules; and connecting a 360 pin female connector on said backplane printed circuit board with a 360 pin male connector on said CPU.
- 11. The method of claim 7, further including mounting a plurality of interface cards in interface card slots in said plurality of interface modules.
- 12. The method of claim 11, wherein said printed circuit board powers down said interface modules including said interface cards thereon.
- 13. A method of electrically coupling a plurality of interface modules to a CPU such that at least one of the interface modules can be removed without powering down the remaining interface modules or the CPU, said method comprising:
mounting a backplane printed circuit board on the back of a chassis; connecting a CPU module to said backplane printed circuit board when mounting a CPU module on said chassis; and removably mounting a plurality of interface modules to the backplane printed circuit board; and connecting the plurality of interface modules to the backplane printed circuit board with bus adapter chips configured to proved arbitrated access to said interface modules and electrical termination and isolation between the interface modules and the CPU module when a interface module is removed.
- 14. The method of claim 13, where said act of connecting said interface module to said backplane printed circuit board comprises the act of connecting a high density connector of said interface module to a high density connector on said backplane printed circuit board.
- 15. The method of claim 14, further including mounting a plurality of interface cards in interface card slots in said plurality of interface modules.
- 16. A system for electrically coupling a central processing unit (CPU) of a server to a plurality of interface modules, the system comprising:
means routing an I/O bus having a first format from said central processing unit to primary sides of a plurality of bus adapter chips; and means for routing an I/O bus of said first format from secondary sides of said bus adapter chips to respective ones of said interface modules.
- 17. The system of claim 16, wherein the bus adapter chips comprise electrical hardware which provides arbitered access along the I/O busses.
- 18. The system of claim 16, wherein the means for routing the I/O buses to and from bus adapter chips comprise means for electrically isolating the CPU from electrical disruption when one of the interface modules is removed.
- 19. The system of claim 16, further including means for mounting a plurality of interface cards in interface card slots in said plurality of interface modules.
- 20. The system of claim 16, further including means for removably mounting said interface modules on a chassis.
RELATED APPLICATIONS
[0001] The present application is a continuation of and claims priority under 35 U.S.C. § 120 to co-pending U.S. patent application Ser. No. 10/016,296, filed Oct. 30, 2001, which is a continuation of U.S. patent application Ser. No. 08/943,044, filed on Oct. 1, 1997.
[0002] Moreover, the benefit under 35 U.S.C. § 119(e) of the following U.S. provisional applications is hereby claimed:
1ApplicationTitleNo.Filing Date“Hardware and Software Architecture for60/047,016May 13, 1997Inter-Connecting an Environmental ManagementSystem with a Remote Interface”“Self Management Protocol for a Fly-By-Wire60/046,416May 13, 1997Service Processor”“Isolated Interrupt Structure for Input/Output60/047,003May 13, 1997Architecture”“Three Bus Server Architecture with a Legacy PCI60/046,490May 13, 1997Bus and Mirrored I/O PCI Buses”“Computer System Hardware Infrastructure for60/046,398May 13, 1997Hot Plugging Single and Multi-Function PC CardsWithout Embedded Bridges”“Computer System Hardware Infrastructure for60/046,312May 13, 1997Hot Plugging Multi-Function PCI Cards WithEmbedded Bridges”
[0003] The subject matter of U.S. Pat. No. 6,175,490 entitled “FAULT TOLERANT COMPUTER SYSTEM”, issued on Jan. 16, 2001, is related to this application.
Provisional Applications (6)
|
Number |
Date |
Country |
|
60047016 |
May 1997 |
US |
|
60046416 |
May 1997 |
US |
|
60047003 |
May 1997 |
US |
|
60046490 |
May 1997 |
US |
|
60046398 |
May 1997 |
US |
|
60046312 |
May 1997 |
US |
Continuations (2)
|
Number |
Date |
Country |
Parent |
10016296 |
Oct 2001 |
US |
Child |
10808220 |
Mar 2004 |
US |
Parent |
08943044 |
Oct 1997 |
US |
Child |
10016296 |
Oct 2001 |
US |