Method of resistor matching in analog integrated circuit layout

Abstract

A method of resistor matching in analog integrated circuit layout is disclosed. Shapes of mismatching resistor blocks are analyzed to obtain geometrical information for deforming the mismatching resistor blocks. The mismatching resistor blocks are deformed into centrosymmetrical blocks according to the obtained geometrical information, each mismatching resistor block being decomposed to a plurality of unit-resistors. The unit-resistors are placed into matching resistor blocks to return a resulting layout with improved matching quality by reducing centroid offset between a centroid of the unit-resistors and a centroid of the matching resistor block.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to analog integrated circuit layout, and more particularly to a nonlinear optimization method for resistor matching in analog integrated circuits.

2. Description of Related Art

Integrated circuit (IC) layout is a representation of an integrated circuit in terms of planar geometric shapes corresponding to layer patterns of the integrated circuit. The key performance of modern analog integrated circuits, such as digital-to-analog converters (DACs), is related to the accuracy of resistance ratios. Severe distortion will present between the input and output signals if the resistors in the analog ICs are mismatched. Due to the cost issue, designers usually design an IC under the strict fixed-outline constrains. To fit the whole design into the fixed-sized chip, devices with low shape flexibility, such as macros and IPs, are placed first. After that, resistors with high shape flexibility are placed in the remaining space. However, the remaining space for resistors is usually in rectilinear shape rather than rectangular shape, and the resistors placement thus becomes a challenge of layout engineers. FIG. 1A shows a layout with a resistor block A according to a conventional method. FIG. 1B shows an enlarged view of the resistor block that is composed of three local matching resistor blocks with their associated centroids, and therefore the resistor block A as a whole commonly does not have high matching quality.

Although several works have studied the detail about the matching methodologies, however, none of the existing works has proposed a methodology to consider matching quality and fixed-outline constraint simultaneously.

Accordingly, a need has thus arisen to propose a novel method of resistor matching in analog integrated circuit layout to effectively improve matching quality and conform to fixed-outline constraint.

SUMMARY OF THE INVENTION

In view of the foregoing, the embodiment of the present invention provides a method of resistor matching in analog integrated circuit layout to improve matching quality of the decomposed matching structures in rectilinear blocks, while maintaining the block topology during the whole improving process in order not to change the original circuit property.

According to one embodiment, shapes of mismatching resistor blocks are analyzed to obtain geometrical information for deforming the mismatching resistor blocks. The mismatching resistor blocks are deformed into centrosymmetrical blocks according to the obtained geometrical information, each said mismatching resistor block being decomposed to a plurality of unit-resistors. The unit-resistors are placed into matching resistor blocks to return a resulting layout with improved matching quality by reducing centroid offset between a centroid of the unit-resistors and a centroid of the matching resistor block.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows a layout with a resistor block according to a conventional method;

FIG. 1B shows an enlarged view of the resistor block of FIG. 1A;

FIG. 2 shows a flow diagram generally illustrating a method of resistor matching in analog integrated circuit layout according to one embodiment of the present invention;

FIG. 3 shows an exemplary mismatching resistor block with two decomposed unit-resistors;

FIG. 4A and FIG. 4B exemplify evaluating the degree of centrosymmetry of a block;

FIG. 5A through FIG. 5D specifically show the matching analysis stage of FIG. 2;

FIG. 6 shows a flow diagram illustrating the matching deformation stage of FIG. 2 according to one embodiment of the present invention; and

FIG. 7A through FIG. 7D show examples that demonstrate deforming mismatching resistor blocks to matching resistor blocks after applying the embodiment.

DETAILED DESCRIPTION OF THE INVENTION

An embodiment of the present invention discloses a nonlinear optimization method for resistor matching in analog integrated circuits. According to one aspect of the embodiment, i.e., a coincidence rule, centers of constituent resistors (or unit-resistors) may be coincided at a centroid of a matching resistor block (that is deformed from a mismatching resistor block). According to another aspect of the embodiment, i.e., a dispersion rule, the unit-resistors of the common-centroid matching resistor block may be placed uniformly. Accordingly, matching quality of a matching resistor block in a layout may be evaluated in terms of both the degree of coincidence and the degree of dispersion. In this specification, let NB={NB₁, NB₂, . . . , NB_n} denote a set of n normal blocks which are soft (or deformable) blocks and each element NB_i in NB has its specific aspect ratio range AS_i=[AS_i—min,AS_i—max]. If the AS_i—min is equal to AS_i—max, this means that the block NB_i is a hard (or undeformable) block. Let MB={MB₁, MB₂, . . . , MB_m} denote a set of m mismatching resistor blocks which are rectilinear blocks (each having more than four sides) to be matched. The disclosed embodiment can improve the matching quality of each mismatching resistor block in MB under fixed-outline constraint. The embodiment can also maintain the block topology in an initial layout L during the process such that the designed circuit features will not be changed. Therefore, no extra cost for redesigning the circuit features will be needed.

FIG. 2 shows a flow diagram generally illustrating a method of resistor matching in analog integrated circuit layout according to one embodiment of the present invention. In stage 1, shapes of the mismatching resistor blocks are analyzed to obtain geometrical information for deforming the mismatching resistor blocks. Subsequently, in stage 2, according to the obtained geometrical information, a nonlinear optimization technique is applied to deform the mismatching resistor blocks into centrosymmetrical blocks which are appropriate for obtaining better matching. Finally, in stage 3, the unit-resistors are assigned into modified mismatching resistor blocks, that is, matching resistor blocks, to return a resulting layout with improved matching quality.

The embodiment improves matching quality by reducing centroid offset between a centroid of the constituent resistors (or unit-resistors) and a centroid of the matching resistor block. FIG. 3 shows an exemplary mismatching resistor block MB_i with two decomposed unit-resistors A. The matching quality (or centrosymmetry) is low because there exists substantial centroid offset between the centroid 31 of the unit-resistors A and the centroid 32 of the mismatching resistor block MB_i. As exemplified in FIG. 4A and FIG. 4B, the degree of centrosymmetry of a (mismatching resistor) block may be evaluated by rotating the block 180 degrees and then comparing the rotated block to the original block. More overlapping between a block and its rotated one implies more centrosymmetry. The block exemplified in FIG. 4A has low degree of centrosymmetry because of low overlap between the block and its rotated one. The block exemplified in FIG. 4B, however, has high degree of centrosymmetry because of high overlap between the block and its rotated one.

FIG. 5A through FIG. 5D specifically show the matching analysis stage 1 of FIG. 2. Although the analysis process of vertical edges of a mismatching resistor block is illustrated in the figures, the analysis process of horizontal edges of the mismatching resistor block, however, is similar and is thus omitted for brevity. As shown in FIG. 5A, two mirrored blocks MB_i—1 and MB_i—r of MB_i are placed to the left and right sides of the mismatching resistor MB_i. All the end points 51, excluding the top and bottom end points, of the right-side vertical edges of the left mirrored block MB_i—1 and the left-side vertical edges of the right mirrored block MB_i—r are projected to the mismatching resistor block MB_i. The projected points on MB_i are called cut points 52.

After obtaining the cut points 52, the mismatching resistor block MB_i is decomposed by horizontally cut through end points 51 of its vertical edges and the cut points 52 (FIG. 5B), resulting in decomposed rectangles Rect_MB—i={rect_i—1, rect_i-2, rect_i-3} (FIG. 5C), which will be used later for deformation. Moreover, all left-side vertical edges of the rectangles are collected as E_i—L={e_i—1, e_i—1—2, . . . , e_i—1—n}, and all right-side vertical edges of the rectangles are collected as E_i—R={e_i—r—1, e_i—r—2, . . . , e_i—r—n}. Subsequently, one edge from E_i—L from top to bottom and one edge from E_i—R from bottom to top are taken as a centrosymmetry pair. Repeat above process until the edges in E_i—L and E_i—R are totally paired. All the centrosymmetry pairs of MB; form a set CS-pairs_MB—i. As exemplified in FIG. 5D, three centrosymmetry pairs {e_i—1—1,e_i—r—3}, {e_i—1—2,e_i—r—2} and {e_i—1—3,e_i—r—1} are formed. As the distances (d₁, d₂, d₃) to the centroid of the block of the two edges in each centrosymmetry pair are the same, the block is a centrosymmetrical block.

Subsequently, in the matching deformation stage 2 (FIG. 2), the shapes of the mismatching resistor blocks will be modified, under the fixed-outline constrains, to centrosymmetrical blocks for improving the matching quality, and, simultaneously, the original block topology in the layout should be preserved in order not to destroy the circuit features which were designed in early stages (not shown).

FIG. 6 shows a flow diagram illustrating the matching deformation stage 2 according to one embodiment of the present invention. In step 21, all blocks in the normal block set NB and all rectangles of each mismatching resistor block in MB are limited not to exceed the coverage (i.e., width W and height H) of the layout:x_i+w_i≦W, ∀NB_iεNB y_i+h_i≦H, ∀NB_iεNB x_i—a+w_i—a≦W, ∀rect_i—aεRect_MB—i, ∀MB_iεMB y_i—a+h_i—a≦H, ∀rect_i—aεRect_MB—i, ∀MB_iεMB where (x_i,y_i) is the lower left corner of a block_i, w_i and h_i are width and height of the block, (x_i—a,y_i—a) is the lower left corner of a rectangle rect_i—a of MB_i, w_i—a and h_i—a are width and height of the rectangle.

In step 22, the range of width of each NB_i is constrained and the area a_i of NB_i in NB is kept consistent after deformation:a_i/AS_i—max≦w_i≦a_i/AS_i—min, ∀NB_iεNB w_i·h_i=a_i, ∀NB_iεNB

In step 23, the positions of the blocks in NB are limited such that their relative positions arc not changed after deformation:x_i+w_i≦x_j, ∀NB_iεNB y_i+h_i≦y_j, ∀NB_iεNB

In step 24, each neighboring normal block of the mismatching resistor block is limited not overlap with MB_j. Take left side as example:x_i+w_i≦x_j—a+B_i,j—a,1·W, ∀NB_iεNB_left, ∀rect_j—aεRect_MB—j, B_i,j—a,1 is binary|(y_i+h_i/2)−(y_a+h_a/2)≧(h_i/2+h_a/2)−B_i,j—a,2·H, ∀NB_iεNB_left, ∀rect_j—aεRect_MB—j, B_i,j—a,2 is binary0≦B_i,j—a,1+B_i,j—a,2≦1

In step 25, rectangles of a mismatching resistor block should be connected:x_i—a+w_i—a≧x_i—b, rect_i—a, rect_i—bεRect_MB—i x_i—b+w_i—b≧x_i—a, rect_i—a, rect_i—bεRect_MB—i y_i—a+h_i—a=y_i—b, rect_i—a, rect_i—bεRect_MB—i

Finally, in step 26, the area a_MB—i of each MB_i in MB is kept consistent after deformation:Σ_rect—i—aεRect_—MB—iw_i—a·h_i—a=a_MB—i, ∀MB_iεMB

Regarding the unit-resistor placement stage 3 of FIG. 2, one unit-resistor is first removed from the mismatching resistor block, if there are odd number of unit-resistors. Subsequently, the removed unit-resistor is then placed at the center of the modified block. Accordingly, the remaining unit-resistors of the same resistor block will be perfectly paired, and each pair of the unit-resistors is then placed centrosymmetrically to the centroid of matching resistor block. The degree of coincidence of the resistor block will be improved after this assignment.

Moreover, two unit-resistors from different resistors may be randomly selected, and their positions being exchanged, and their corresponding centrosymmetrical unit-resistors are also exchanged. The exchange may be repeated until the degree of dispersion can no longer be enhanced.

According to the embodiment as discussed above, the matching quality may be substantially improved by deforming the mismatching resistor block into a centrosymmetrical block which is more appropriate for matching than arbitrary rectilinear block. FIG. 7A and FIG. 7B show an example that demonstrates deforming a mismatching resistor block (FIG. 7A) to a rectangular block (FIG. 7B) after applying the embodiment. FIG. 7C and FIG. 7D show another example that demonstrates deforming a mismatching resistor block (FIG. 7C) to a centrosymmetrical block (FIG. 7D) after applying the embodiment.

Although specific embodiments have been illustrated and described, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present invention, which is intended to be limited solely by the appended claims.

Claims

1. A method of resistor matching in analog integrated circuit layout, comprising the following stages: analyzing shapes of mismatching resistor blocks to obtain geometrical information for deforming the mismatching resistor blocks;deforming the mismatching resistor blocks into centrosymmetrical blocks according to the obtained geometrical information, each said mismatching resistor block being decomposed to a plurality of unit-resistors; andplacing the unit-resistors into matching resistor blocks to return a resulting layout with improved matching quality by reducing centroid offset between a centroid of the unit-resistors and a centroid of the matching resistor block;wherein a step of evaluating degree of centrosymmetry of the mismatching resistor block is performed by rotating the mismatching resistor block 180 degrees and then comparing the rotated mismatching resistor block to the original mismatching resistor block.

2. The method of claim 1, wherein the matching stage comprises: generating two mirrored blocks of the mismatching resistor block;projecting end points, excluding outermost end points, of edges of the mirrored blocks to the mismatching resistor block, thereby resulting in cut points;decomposing the mismatch resistor block by horizontally or vertically cut through the end points and the cut points of edges of the mismatch resistor block, resulting in decomposed rectangles, wherein first-side edges of the rectangles are collected as a first set and second-side edges of the rectangles are collected as a second set;taking one edge from the first set from beginning to end and taking one edge from the second set from end to beginning as a centrosymmetry pair; andrepeating the pairing step until the edges in the first set and the second set are totally paired.

3. The method of claim 2, wherein the deforming stage comprises: modifying shapes of the mismatching resistor blocks, under fixed-outline constrains, to the centrosymmetrical blocks; andpreserving original block topology in an original layout in order not to destroy circuit features.

4. The method of claim 2, wherein the placing stage comprises: limiting all normal blocks and all the rectangles of the mismatching resistor block not to exceed width and height of the layout;constraining range of width of the normal block and keeping area of the normal block consistent after deformation;limiting positions of the normal blocks such that their relative positions are not changed after deformation;limiting each neighboring normal block of the mismatching resistor block not overlap therewith;connecting the rectangles of the mismatching resistor block; andkeeping area of the mismatching resistor block consistent after deformation.

5. The method of claim 4, wherein the placing stage comprises: first removing one said unit-resistor from the mismatching resistor block, if there are odd number of the unit-resistors;placing the removed unit-resistor at the center of the matching resistor block; andplacing each pair of the unit-resistors centrosymmetrically to the centroid of the matching resistor block.

6. The method of claim 5, further comprising: randomly selecting two said unit-resistors from different mismatching resistor blocks and then exchanging positions of the selected unit-resistors; andexchanging positions of corresponding unit-resistors of the selected unit-resistors.