Claims
- 1. A method of severing a semiconductor wafer with a multiplicity of optoelectronic semiconductor structures into a plurality of individual chips, which comprises:providing a semiconductor wafer with a multiplicity of optoelectronic semiconductor structures; depositing a covering layer of photoresist material over an entire surface of the semiconductor wafer with the optoelectronic semiconductor structures; structuring the covering layer and partly removing the covering layer to define cutting tracks; guiding an abrasive cutting tool along the cutting tracks by moving the cutting tool and the semiconductor wafer relative to one another and thereby cutting the semiconductor wafer along the cutting tracks into individual chips; subsequently etching chip flanks of the chips; and removing the covering layer.
- 2. The method according to claim 1, wherein the structuring step comprises structuring the covering layer by a phototechnical exposure process with a photomask and a subsequent developing process.
- 3. The method according to claim 1, wherein the depositing step comprises covering the entire surface of the semiconductor wafer at a thickness of at least substantially 5 μm.
- 4. The method according to claim 1, wherein the providing step comprises providing a semiconductor wafer with a III-V semiconductor as a base material.
- 5. The method according to claim 4, wherein the semiconductor wafer has a base material selected from the group consisting of GaAlAs and InP.
- 6. The method according to claim 1, wherein the optoelectronic semiconductor structures are diode structures produced in the semiconductor wafer.
- 7. The method according to claim 1, wherein the optoelectronic semiconductor structures are light-emitting diodes.
Priority Claims (1)
Number |
Date |
Country |
Kind |
196 32 815.2 |
Aug 1996 |
DE |
|
CROSS-REFERENCE TO RELATED APPLICATION
This is a continuation of copending International Application PCT/DE97/01756, filed Aug. 14, 1997, which designated the United States.
US Referenced Citations (3)
Number |
Name |
Date |
Kind |
4476620 |
Ohki et al. |
Oct 1984 |
|
4731344 |
Canning et al. |
Mar 1988 |
|
5171176 |
Cagan et al. |
Dec 1992 |
|
Foreign Referenced Citations (2)
Number |
Date |
Country |
0 661 737 A1 |
Jul 1995 |
EP |
61-180442 |
Aug 1986 |
JP |
Non-Patent Literature Citations (3)
Entry |
Patent Abstracts of Japan No. 08-064557 A (Shoichi), dated Mar. 8, 1996. |
Patent Abstracts of Japan No. 07-161665 A (Noburu), dated Jun. 23, 1995. |
“A Hybrid Wafer-Dicing Process of GaAs MMIC Production” (Chang et al.), IEEE Transactions on Semiconductor Manufacturing, vol. 4, No. 1, Feb. 1991. |
Continuations (1)
|
Number |
Date |
Country |
Parent |
PCT/DE97/01756 |
Aug 1997 |
US |
Child |
09/250866 |
|
US |