Claims
- 1. A method of fabricating a semiconductor resistor comprising:providing a FLASH memory cell gate stack on an insulating region of a semiconductor substrate, said gate stack comprising, a floating gate, an interpoly dielectric layer on said floating gate, and a control gate film on said interpoly dielectric layer; removing said control gate film from over said interpoly dielectric leaving a region of said control gate film only along the perimeter of said interpoly dielectric; and forming electrical contacts to said floating gate to form a resistor.
- 2. The method of claim 1 wherein said removing said control gate film comprises a photolithographic process and a polysilicon etch process.
- 3. The method of claim 1 wherein said floating gate is polysilicon.
- 4. The method of claim 1 wherein said control gate is polysilicon.
- 5. The method of claim 1 wherein said interpoly dielectric comprises alternating layers of silicon oxide and silicon nitride.
- 6. A method of fabricating a semiconductor resistor in embedded FLASH memory applications comprising:providing a FLASH memory cell gate stack on an insulating region of a semiconductor substrate containing at least one MOS transistor region, said FLASH memory cell gate stack comprising, a floating gate, an interpoly dielectric layer on said floating gate, and a control gate film on said interpoly dielectric layer and said MOS transistor region; simultaneously forming a gate electrode on said MOS transistor by etching control gate film and removing said control gate film from over said interpoly dielectric layer leaving a region of said control gate film only along the perimeter of said interpoly dielectric; and forming electrical contacts to said floating gate to form a resistor.
- 7. The method of claim 6 wherein simultaneously forming said gate electrode on said MOS transistor comprises etching a polysilicon film to define said gate electrode.
- 8. The method of claim 6 wherein said simultaneously forming said gate electrode on said MOS transistor comprises a photolithographic process and a polysilicon etch process.
- 9. The method of claim 6 wherein said floating gate is polysilicon.
- 10. The method of claim 6 wherein said control gate film is polysilicon.
- 11. The method of claim 6 wherein said interpoly dielectric comprises alternating layers of silicon oxide and silicon nitride.
Parent Case Info
This application claims benefit of provisional applications 60/143,398 filed Jul. 12, 1999. 60/068,543 filed Dec. 23, 1997, and 60/117,774 filed Jan. 29, 1999.
US Referenced Citations (5)
Provisional Applications (3)
|
Number |
Date |
Country |
|
60/143398 |
Jul 1999 |
US |
|
60/117774 |
Jan 1999 |
US |
|
60/068543 |
Dec 1997 |
US |