Claims
- 1. A method of fabricating an embedded FLASH integrated circuit comprising:forming a first photoresist film over a semiconductor substrate; patterning said first photoresist film to expose a first region of a polycrystalline silicon film where a control gate will be formed in a FLASH memory cell and masking a second region of said polycrystalline silicon film wherein said second region of said polycrystalline silicon film region will be used to form a gate structure of a NMOS transistor and a gate structure of a PMOS transistor; and partially etching said first region of said polycrystalline silicon film.
- 2. The method of claim 1 wherein said partially etching said first region of said polycrystalline silicon film comprises removing about 20% of a initial film thickness of said polycrystalline silicon film.
- 3. The method of claim 1 wherein said partially etching said first region of said polycrystalline silicon film comprises using a HBr/Cl2/CF4/HeO2 plasma etch process.
- 4. The method of claim 1 further comprising the steps of:removing said first photoresist film; forming and patterning a second photoresist film; and etching said polycrystalline silicon film to simultaneously form a FLASH memory cell gate stack structure, said gate structure of said NMOS transistor and said gate structure of said PMOS transistor.
- 5. A method of fabricating an embedded FLASH integrated circuit comprising:forming a first photoresist film over a semiconductor substrate; patterning said first photoresist film to expose a first region of a polycrystalline silicon film where a control gate will be formed in a FLASH memory cell and masking a second region of said polycrystalline silicon film wherein said second region of said polycrystalline silicon film region will be used to form a gate structure of a NMOS transistor and a gate structure of a PMOS transistor; partially etching said first region of said polycrystalline silicon film; removing said first photoresist film; forming and patterning a second photoresist film; and etching said polycrystalline silicon film to simultaneously form a FLASH memory cell gate stack structure, said gate structure of said NMOS transistor and said gate structure of said PMOS transistor.
- 6. The method of claim 5 wherein said partially etching said first region of said polycrystalline silicon film comprises removing about 20% of a initial film thickness of said polycrystalline silicon film.
- 7. The method of claim 5 wherein said partially etching said first region of said polycrystalline silicon film comprises using a HBr/Cl2/CF4/HeO2 plasma etch process.
- 8. A method of simultaneously forming FLASH memory cell gate stacks and NMOS and PMOS gate structures on an embedded integrated circuit comprising:forming a first photoresist film over a semiconductor substrate; patterning said first photoresist film to expose a first region of a polycrystalline silicon film where a control gate will be formed in a FLASH memory cell and masking a second region of said polycrystalline silicon film wherein said second region of said polycrystalline silicon film region will be used to form a gate structure of a NMOS transistor and a gate structure of a PMOS transistor; implanting said first region of said polycrystalline silicon film with a n-type dopant species; partially etching said first region of said polycrystalline silicon film; removing said first photoresist film; forming and patterning a second photoresist film; and etching said polycrystalline silicon film to simultaneously form a FLASH memory cell gate stack structure, said gate structure of said NMOS transistor and said gate structure of said PMOS transistor.
- 9. The method of claim 8 wherein said partially etching said first region of said polycrystalline silicon film comprises removing about 20% of a initial film thickness of said polycrystalline silicon film.
- 10. The method of claim 8 wherein said partially etching said first region of said polycrystalline silicon film comprises using a HBr/Cl2/CF4/HeO2 plasma etch process.
- 11. The method of claim 8 wherein said etching said polycrystalline silicon film to simultaneously form a FLASH memory cell gate stack structure, said gate structure of said NMOS transistor and said gate structure of said PMOS transistor is a multiple step process, comprising:a control gate etch comprising a HBr/Cl2/CF4/HeO2 based plasma etch; a CHF3/O2 based plasma interpoly dielectric etch; a HBr/Cl2/HeO2 plasma based gate etch; and a HBr/HeO2 based plasma over etch.
CROSS-REFERENCE TO RELATED PATENT/PATENT APPLICATIONS
This application claims benefit to Provisional Application 60/152,879 filed Sep. 8, 1999.
The following commonly assigned patent/patent applications are hereby incorporated herein by reference:
US Referenced Citations (3)
Number |
Name |
Date |
Kind |
5879990 |
Dormans et al. |
Mar 1999 |
A |
6207991 |
Rahim |
Mar 2001 |
B1 |
6274430 |
Jan et al. |
Aug 2001 |
B1 |
Foreign Referenced Citations (1)
Number |
Date |
Country |
1069614 |
Jan 2001 |
EP |
Provisional Applications (1)
|
Number |
Date |
Country |
|
60/152879 |
Sep 1999 |
US |