Patent Application
20080091875
In order that the advantages of the invention will be readily understood, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the invention and are not therefore to be considered to be limiting of its scope, the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings, in which:
Some of the functional units described in this specification have been labeled as modules in order to more particularly emphasize their implementation independence. For example, a module may be implemented as a hardware circuit comprising custom VLSI circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. A module may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices, or the like.
Modules may also be implemented in software for execution by various types of processors. An identified module of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions which may, for instance, be organized as an object, procedure, or function. Nevertheless, the executables of an identified module need not be physically located together, but may comprise disparate instructions stored in different locations which, when joined logically together, comprise the module and achieve the stated purpose for the module.
Indeed, a module of executable code may be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, and across several memory devices. Similarly, operational data may be identified and illustrated herein within modules, and may be embodied in any suitable form and organized within any suitable type of data structure. The operational data may be collected as a single data set, or may be distributed over different locations including over different storage devices, and may exist, at least partially, merely as electronic signals on a system or network.
Reference throughout this specification to “one embodiment,” “an embodiment,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.
Reference to a signal bearing medium may take any form capable of generating a signal, causing a signal to be generated, or causing execution of a program of machine-readable instructions on a digital processing apparatus. A signal bearing medium may be embodied by a transmission line, a compact disk, digital-video disk, a magnetic tape, a Bernoulli drive, a magnetic disk, a punch card, flash memory, integrated circuits, or other digital processing apparatus memory device.
The schematic flow chart diagrams included are generally set forth as logical flow-chart diagrams. As such, the depicted order and labeled steps are indicative of one embodiment of the presented method. Other steps and methods may be conceived that correspond in function, logic, or effect to one or more steps, or portions thereof, of the illustrated method. Additionally, the format and symbols employed are provided to explain the logical steps of the method and are understood not to limit the scope of the method. Although various arrow types and line types may be employed in the flow-chart diagrams, they are understood not to limit the scope of the corresponding method. Indeed, some arrows or other connectors may be used to indicate only the logical flow of the method. For instance, an arrow may indicate a waiting or monitoring period of unspecified duration between enumerated steps of the depicted method. Additionally, the order in which a particular method occurs may or may not strictly adhere to the order of the corresponding steps shown.
Furthermore, the described features, structures, or characteristics of the invention may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided, such as examples of programming, software modules, user selections, network transactions, database queries, database structures, hardware modules, hardware circuits, hardware chips, etc., to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
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Reference to a “background” stage refers to an executing thread 30 which is run in the background or on a separate executing thread that the cache manager module 18 may be executing at a particular time. As a result of invoking a stage operation, all non-contiguous sectors in a particular track are filled with unmodified data. Because an affected track which has underwent a background stage operation has all sectors which are then filled, an entire image of data can be constructed when incorporating the particular data into a write command. The full track is essentially now in cache.
Following a full background stage operation, the full track can be written to disk 8 or a similar storage medium with a single write command. For example, the full track can then be destaged to disk following an LRU algorithm previously described. This replaces the necessity of having to construct a single sector write command for every other modified sector in a track not subjected to the present invention.
Again, the present invention increases host write and destage performance of modified tracks with a large number of non-contiguous sectors or holes by calculating the number of holes in the track at the completion of each cache write operation. If a large number of holes are present, a full track stage of the track is issued in the background. Following the completion of the background stage, subsequent write performance is improved because what were sector misses are now cache hits. Destage performance is also increased since the destage is now a full track write to the disks.
At the completion of a cache write operation, a count of the number of holes in the track is calculated. If the number of holes calculated on the track is greater than a predetermined threshold, a fill track background stage is issued. Since the full track is now in cache, subsequent writes to the track are faster, since they are now cache hits. Destage performance is improved since the full track can either be grouped for a full stride write, or, if the track is destaged by itself, the track can be implemented using a full track write instead of a plurality of single sector writes.
Software and/or hardware to implement the method previously described, such as the described full background stage, can be created using tools currently known in the art. The implementation of the described system and method involves no significant additional expenditure of resources or additional hardware than what is already in used in many storage subsystems, making the implementation cost-effective.
Implementing and utilizing the example systems and methods as described can provide a simple, effective method of increasing performance in a computer system featuring a cache storage subsystem. While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.
