Claims
- 1. A method for analyzing an integrated circuit (IC) having at least one of the group consisting of digital and analog components, wherein the IC is designed to meet a plurality of circuit performance specifications, and fabrication of the IC is monitored by measuring process factors and a previously defined set of electrical test variables, the method comprising the steps of:
(a) forming a set of linearly independent electrical test parameters based on a subset of the set of electrical test variables; (b) mapping the set of process factors to the linearly independent electrical test parameters; (c) forming a plurality of figure-of-merit (FOM) performance models based on the process factors; and (d) combining the FOM models with the mapping to enable modeling of IC performance based on the linearly independent electrical test parameters.
- 2. The method of claim 1, wherein step (a) includes:
(i) detecting at least two of the set of electrical test variables that provide redundant information; (ii) forming a subset of the set of electrical test variables, excluding from the subset at least one of the detected variables; (iii) transforming the subset of electrical tests to the set of linearly independent principle components.
- 3. The method of claim 2, wherein the detecting step includes detecting at least two of the set of electrical test variables that are highly correlated with each other.
- 4. The method of claim 2, wherein step (iii) includes performing a principle component transformation.
- 5. The method of claim 4, wherein the principle component transformation includes at least one of the group consisting of QR decomposition, singular value decomposition and LU factorization.
- 6. The method of claim 1, wherein the FOM models are response surface methodology models.
- 7. The method of claim 1, wherein the FOM models include at least one of the group consisting of quadratic performance models and linear performance models.
- 8. The method of claim 1, further comprising:
selecting a plurality of different designs of experiment (DOE) based on respective combinations of the process factors; generating a respective response FOM model for each DOE; and analyzing sensitivity of circuit performance to each of the process factors.
- 9. The method of claim 8, further comprising:
adding at least one additional electrical test to the set of electrical test variables, based on the sensitivity analysis.
- 10. The method of claim 9, further comprising repeating steps (a) through (d)
- 11. A method for analyzing an integrated circuit (IC) having digital and analog components, wherein the IC is designed to meet a plurality of circuit performance specifications, and fabrication of the IC is monitored by measuring process factors and a previously defined set of electrical test variables, the method comprising the steps of:
(a) detecting at least two of the set of electrical test variables that that are highly correlated with each other; (b) forming a subset of the set of electrical test variables, excluding from the subset at least one of the detected variables; (c) transforming the subset of electrical tests by a principle component transformation to a set of linearly independent principle components; (d) mapping the set of process factors to the linearly independent electrical test parameters; (e) forming a plurality of figure-of-merit (FOM) performance response surface methodology models based on the process factors; and (f) combining the FOM models with the mapping to enable modeling of IC performance based on the linearly independent electrical test parameters.
- 12. The method of claim 11, further comprising:
selecting a plurality of different designs of experiment (DOE) based on respective combinations of the process factors; generating a respective response FOM model for each DOE; and analyzing sensitivity of circuit performance to each of the process factors.
- 13. The method of claim 12, further comprising:
adding at least one additional electrical test to the set of electrical test variables, based on the sensitivity analysis.
- 14. The method of claim 13, further comprising repeating steps (a) through (d)
Parent Case Info
[0001] This application claims the benefit of U.S. Provisional Patent Application No. 60/347,642, filed Jan. 10, 2002.
Provisional Applications (1)
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Number |
Date |
Country |
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60347642 |
Jan 2002 |
US |