as a result of hardware simulation

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CPC
G01R31/318364

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

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G01R31/318364as a result of hardware simulation

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Reduced signaling interface method and apparatus
- Patent number 11,867,756
- Issue date Jan 9, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with reduced signaling interface
- Patent number 11,768,238
- Issue date Sep 26, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data traffic injection for simulation of circuit designs
- Patent number 11,630,935
- Issue date Apr 18, 2023
- Xilinx, Inc.
- Amit Kasat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical access simulation for signaling with more than two sta...
- Patent number 11,543,452
- Issue date Jan 3, 2023
- Xilinx, Inc.
- Saikat Bandyopadhyay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced signaling interface circuit
- Patent number 11,519,959
- Issue date Dec 6, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Entering home state after soft reset signal after address match
- Patent number 11,079,431
- Issue date Aug 3, 2021
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Automatic testbench generator for test-pattern validation
- Patent number 11,036,907
- Issue date Jun 15, 2021
- Synopsys, Inc.
- Slimane Boutobza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for accelerating timing-accurate gate-level logic...
- Patent number 10,794,954
- Issue date Oct 6, 2020
- Avery Design Systems, Inc.
- Kai-Hui Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low cost design for test architecture
- Patent number 10,712,388
- Issue date Jul 14, 2020
- Chinsong Sul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mapping physical shift failures to scan cells for detecting physica...
- Patent number 10,605,863
- Issue date Mar 31, 2020
- Synopsys, Inc.
- Subhadip Kundu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System architecture method and apparatus for adaptive hardware faul...
- Patent number 10,495,691
- Issue date Dec 3, 2019
- NXP USA, INC.
- Xiao Sun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for performing a scalability check on a hardwa...
- Patent number 10,345,378
- Issue date Jul 9, 2019
- ARM Limited
- Rakesh Shaji Lal
- G01 - MEASURING TESTING
Information Patent Grant
Low cost design for test architecture
- Patent number 10,338,138
- Issue date Jul 2, 2019
- Chinsong Sul
- G01 - MEASURING TESTING
Information Patent Grant
Address/instruction registers, target domain interfaces, control in...
- Patent number 10,330,729
- Issue date Jun 25, 2019
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using computer-aided design layout in scanning system
- Patent number 10,325,057
- Issue date Jun 18, 2019
- Amber Precision Instruments, Inc.
- Giorgi Muchaidze
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transition test generation for detecting cell internal defects
- Patent number 10,222,420
- Issue date Mar 5, 2019
- Mentor Graphics Corporation
- Xijiang Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and methods for simulating a circuit design
- Patent number 10,210,294
- Issue date Feb 19, 2019
- Xilinx, Inc.
- Kyle Corbett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for validating a test pattern
- Patent number 10,102,329
- Issue date Oct 16, 2018
- NXP USA, INC.
- Yoav Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for performing electrical tests on complex devices
- Patent number 10,048,307
- Issue date Aug 14, 2018
- AIRBUS DEFENCE AND SPACE S.A.
- Josef Ignacio Hotz Ordono
- G01 - MEASURING TESTING
Information Patent Grant
Addressable tap domain selection circuit with instruction and linki...
- Patent number 9,933,483
- Issue date Apr 3, 2018
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generation of test stimuli
- Patent number 9,619,595
- Issue date Apr 11, 2017
- Infineon Technologies AG
- Thomas Nirmaier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
TAP addressable circuit with bi-directional TMS and second signal lead
- Patent number 9,535,118
- Issue date Jan 3, 2017
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing synchronous triggers for waveform capture in an FPGA p...
- Patent number 9,495,492
- Issue date Nov 15, 2016
- Cadence Design Systems, Inc.
- Vasant V. Ramabadran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Generating coverage data for a switch frequency of HDL or VHDL signals
- Patent number 9,405,870
- Issue date Aug 2, 2016
- GLOBALFOUNDRIES Inc.
- Joerg Deutschle
- G01 - MEASURING TESTING
Information Patent Grant
System for and method of semiconductor fault detection
- Patent number 9,390,219
- Issue date Jul 12, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Grant
Modeling test space for system behavior with optional variable comb...
- Patent number 9,262,307
- Issue date Feb 16, 2016
- International Business Machines Corporation
- Itai Segall
- G01 - MEASURING TESTING
Information Patent Grant
Linking circuitry selectively coupling TDI/TDO with first and secon...
- Patent number 9,170,300
- Issue date Oct 27, 2015
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for performing compilation using multiple desi...
- Patent number 9,122,826
- Issue date Sep 1, 2015
- Altera Corporation
- Terry Borer
- G01 - MEASURING TESTING
Information Patent Grant
Address and instruction controller with TCK, TMS, address match inputs
- Patent number 8,892,970
- Issue date Nov 18, 2014
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Bridge fault removal apparatus, bridge fault removal method, and co...
- Patent number 8,886,487
- Issue date Nov 11, 2014
- Kabushiki Kaisha Toshiba
- Yasuyuki Nozuyama
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
REDUCED SIGNALING INTERFACE METHOD & APPARATUS
- Publication number 20230058458
- Publication date Feb 23, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED SIGNALING INTERFACE METHOD & APPARATUS
- Publication number 20210325456
- Publication date Oct 21, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED SIGNALING INTERFACE METHOD & APPARATUS
- Publication number 20210072310
- Publication date Mar 11, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low Cost Design For Test Architecture
- Publication number 20190324083
- Publication date Oct 24, 2019
- Chinsong Sul
- G01 - MEASURING TESTING
Information Patent Application
REDUCED SIGNALING INTERFACE METHOD & APPARATUS
- Publication number 20190265295
- Publication date Aug 29, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System Architecture Method and Apparatus for Adaptive Hardware Faul...
- Publication number 20190250210
- Publication date Aug 15, 2019
- NXP USA, Inc.
- Xiao Sun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR PERFORMING A SCALABILITY CHECK ON A HARDWA...
- Publication number 20190064269
- Publication date Feb 28, 2019
- ARM Limited
- Rakesh SHAJI LAL
- G01 - MEASURING TESTING
Information Patent Application
REDUCED SIGNALING INTERFACE METHOD & APPARATUS
- Publication number 20180172763
- Publication date Jun 21, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods And Systems For Test Power Analysis
- Publication number 20140365148
- Publication date Dec 11, 2014
- Mohammad Tehranipoor
- G01 - MEASURING TESTING
Information Patent Application
SEQUENTIAL LOGIC SENSITIZATION FROM STRUCTURAL DESCRIPTION
- Publication number 20140344637
- Publication date Nov 20, 2014
- Synopsys, Inc.
- Srivathsan Krishna Mohan
- G01 - MEASURING TESTING
Information Patent Application
Multiprocessor Computer System and Method Having at Least One Proce...
- Publication number 20140189619
- Publication date Jul 3, 2014
- FTL Systems, Inc.
- John C. Willis
- G01 - MEASURING TESTING
Information Patent Application
COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER...
- Publication number 20130305200
- Publication date Nov 14, 2013
- Laung-Terng WANG
- G01 - MEASURING TESTING
Information Patent Application
Modeling Test Space for System behavior with Optional Variable comb...
- Publication number 20130091382
- Publication date Apr 11, 2013
- International Business Machines Corporation
- Itai Segall
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND SYSTEM FOR IMPLEMENTING PARALLEL EXECUTION IN A COMPUTIN...
- Publication number 20120316858
- Publication date Dec 13, 2012
- Cadence Design Systems, Inc.
- Kenneth S. Kundert
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND SYSTEM FOR IMPLEMENTING PARALLEL EXECUTION IN A COMPUTIN...
- Publication number 20120253732
- Publication date Oct 4, 2012
- Cadence Design Systems, Inc.
- Kenneth S. Kundert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER...
- Publication number 20120246604
- Publication date Sep 27, 2012
- Syntest Technologies, Inc.
- Laung-Terng (L. -T.) WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Analyzing the Safety of a Device Employing On Target Hard...
- Publication number 20120216091
- Publication date Aug 23, 2012
- ANSALDO STS USA, INC.
- Kevin Joseph Blostic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED SIGNALING INTERFACE METHOD AND APPARATUS
- Publication number 20120216090
- Publication date Aug 23, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGR...
- Publication number 20120124538
- Publication date May 17, 2012
- International Business Machines Corporation
- David E. LACKEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGR...
- Publication number 20120115256
- Publication date May 10, 2012
- International Business Machines Corporation
- David E. LACKEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGR...
- Publication number 20120112341
- Publication date May 10, 2012
- International Business Machines Corporation
- David E. LACKEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR IMPLEMENTING, CONTROLLING, AND INTERFACING WI...
- Publication number 20120038648
- Publication date Feb 16, 2012
- Cadence Design Systems, Inc.
- Kenneth S. Kundert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR IMPLEMENTING CIRCUIT SIMULATORS
- Publication number 20110270556
- Publication date Nov 3, 2011
- Cadence Design Systems, Inc.
- Kenneth S. Kundert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED SIGNALING INTERFACE METHOD & APPARATUS
- Publication number 20110202808
- Publication date Aug 18, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design verification apparatus and design verification program
- Publication number 20110197172
- Publication date Aug 11, 2011
- FUJITSU LIMITED
- Tatsuya Yamamoto
- G01 - MEASURING TESTING
Information Patent Application
COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER...
- Publication number 20110197171
- Publication date Aug 11, 2011
- Syntest Technologies, Inc.
- Laung-Terng (L.-T.) WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED SIGNALING INTERFACE METHOD AND APPARATUS
- Publication number 20110087938
- Publication date Apr 14, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiprocessor Computer System and Method Having at Least One Proce...
- Publication number 20110055516
- Publication date Mar 3, 2011
- FTL Systems Technology Corporation
- John C. Willis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR INTEGRATED CIRCUIT DESIGN VERIFICATION IN A VERIFICATION...
- Publication number 20110055780
- Publication date Mar 3, 2011
- Martti VENELL
- G01 - MEASURING TESTING
Information Patent Application
TEST METHOD, TEST CONTROL PROGRAM AND SEMICONDUCTOR DEVICE
- Publication number 20100332932
- Publication date Dec 30, 2010
- NEC ELECTRONICS CORPORATION
- Hiroyuki MURAOKA
- G01 - MEASURING TESTING

as a result of hardware simulation

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Reduced signaling interface method and apparatus

Integrated circuit with reduced signaling interface

Data traffic injection for simulation of circuit designs

Hierarchical access simulation for signaling with more than two sta...

Reduced signaling interface circuit

Entering home state after soft reset signal after address match

Automatic testbench generator for test-pattern validation

System and method for accelerating timing-accurate gate-level logic...

Low cost design for test architecture

Mapping physical shift failures to scan cells for detecting physica...

System architecture method and apparatus for adaptive hardware faul...

Apparatus and method for performing a scalability check on a hardwa...

Low cost design for test architecture

Address/instruction registers, target domain interfaces, control in...

Using computer-aided design layout in scanning system

Transition test generation for detecting cell internal defects

System and methods for simulating a circuit design

Method and apparatus for validating a test pattern

Method and system for performing electrical tests on complex devices

Addressable tap domain selection circuit with instruction and linki...

Generation of test stimuli

TAP addressable circuit with bi-directional TMS and second signal lead

Implementing synchronous triggers for waveform capture in an FPGA p...

Generating coverage data for a switch frequency of HDL or VHDL signals

System for and method of semiconductor fault detection

Modeling test space for system behavior with optional variable comb...

Linking circuitry selectively coupling TDI/TDO with first and secon...

Method and apparatus for performing compilation using multiple desi...

Address and instruction controller with TCK, TMS, address match inputs

Bridge fault removal apparatus, bridge fault removal method, and co...

Patents Applicationslast 30 patents

REDUCED SIGNALING INTERFACE METHOD & APPARATUS

REDUCED SIGNALING INTERFACE METHOD & APPARATUS

REDUCED SIGNALING INTERFACE METHOD & APPARATUS

Low Cost Design For Test Architecture

REDUCED SIGNALING INTERFACE METHOD & APPARATUS

System Architecture Method and Apparatus for Adaptive Hardware Faul...

APPARATUS AND METHOD FOR PERFORMING A SCALABILITY CHECK ON A HARDWA...

REDUCED SIGNALING INTERFACE METHOD & APPARATUS

Methods And Systems For Test Power Analysis

SEQUENTIAL LOGIC SENSITIZATION FROM STRUCTURAL DESCRIPTION

Multiprocessor Computer System and Method Having at Least One Proce...

COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER...

Modeling Test Space for System behavior with Optional Variable comb...

METHOD AND SYSTEM FOR IMPLEMENTING PARALLEL EXECUTION IN A COMPUTIN...

METHOD AND SYSTEM FOR IMPLEMENTING PARALLEL EXECUTION IN A COMPUTIN...

COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER...

Method of Analyzing the Safety of a Device Employing On Target Hard...

REDUCED SIGNALING INTERFACE METHOD AND APPARATUS

METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGR...

METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGR...

METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGR...

METHOD AND SYSTEM FOR IMPLEMENTING, CONTROLLING, AND INTERFACING WI...

METHOD AND SYSTEM FOR IMPLEMENTING CIRCUIT SIMULATORS

REDUCED SIGNALING INTERFACE METHOD & APPARATUS

Design verification apparatus and design verification program

COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER...

REDUCED SIGNALING INTERFACE METHOD AND APPARATUS

Multiprocessor Computer System and Method Having at Least One Proce...

METHOD FOR INTEGRATED CIRCUIT DESIGN VERIFICATION IN A VERIFICATION...

TEST METHOD, TEST CONTROL PROGRAM AND SEMICONDUCTOR DEVICE