Claims
- 1. A circuit having at least two output conditions during operation in a non-test mode, one of said output conditions being a relatively high impedance condition and another of the output conditions being a first voltage level, comprising:
- means for placing said circuit into a test mode of operation;
- means for receiving an enable signal and for driving an output of said circuit during the test mode to each of a second voltage level that represents the relatively high impedance output condition and the first voltage level, in response to said enable signal, the first and second voltage levels corresponding to predetermined logic levels of said enable signal during proper circuit operation.
- 2. A circuit according to claim 1, wherein said circuit is at least one of an open drain circuit and an open collector circuit.
- 3. A circuit according to claim 1, wherein said circuit is an open drain circuit.
- 4. A circuit according to claim 1, wherein said circuit is an open collector circuit.
- 5. Circuit according to claim 3, wherein said means for driving includes a NOR gate.
- 6. Circuit according to claim 3, wherein said means for driving includes a NAND gate.
- 7. Circuit according to claim 4, wherein said means for driving includes a NOR gate.
- 8. Circuit according to claim 4, wherein said means for driving includes a NAND gate. circuit.
Parent Case Info
This application is a divisional, of Application Ser. No. 08/334,114, filed Nov. 4, 1994, now U.S. Pat. No. 5,471,153.
US Referenced Citations (3)
Divisions (1)
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Number |
Date |
Country |
Parent |
334114 |
Nov 1994 |
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