Claims
- 1. A method of fabricating an integrated circuit, comprising the steps of:
fabricating a plurality of digital transistors using a first pocket implant; and fabricating a first plurality of analog transistors using a second pocket implant having a lower dose than said first pocket implant on at least a source side.
- 2. The method of claim 1, wherein the step of fabricating a plurality of digital transistors comprises the step of using a lightly doped implant to form a drain extension region in said plurality of digital transistors using a first mask and wherein the step of fabricating a first plurality of analog transistors comprises forming a drain extension region in said first plurality of analog transistors using a second mask, wherein said first mask is used for the first pocket implant and the second mask is used for the second pocket implant.
- 3. The method of claim 1, wherein said step of fabricating said first plurality of analog transistors uses said second pocket implant on a drain side of the first plurality of analog transistors and said first pocket implant on a source side of said first plurality of analog transistors.
- 4. The method of claim 1, further comprising the step of forming a second plurality of analog transistors using said second pocket implant on both a drain side and a source side of said second plurality of analog transistors.
- 5. A method of fabricating an integrated circuit, comprising the steps of:
forming a plurality of isolation structures in a semiconductor body; forming a plurality of gate structures over said semiconductor body; implanting a first n-type lightly doped drain region and a first p-type pocket region in a first plurality of digital transistors regions using a first masking layer; implanting a second n-type lightly doped drain region and a second p-type pocket region in at least a drain side of said plurality of analog transistor regions using a second masking layer; and forming a source and drain region in each of said first plurality of digital transistor regions and said plurality of analog transistor regions.
- 6. The method of claim 5, wherein said at least a drain side of said plurality of analog transistor regions includes a source said of at least a subset of said plurality of analog transistor regions.
- 7. The method of claim 5, further comprising the step of implanting a high voltage n-type lightly doped drain region in a second plurality of digital transistors.
- 8. A method of developing a process flow, comprising the steps of:
identifying a plurality of MOS transistor types including both analog and digital transistor types; developing a list of mask levels; for each mask level, identifying which of said plurality of MOS transistor types require the mask level; selecting one or more of said plurality of MOS transistor types; and selecting from said list of mask levels only those mask levels identified as being required by the selected one or more of said plurality of MOS transistors types.
- 9. The method of claim 8, wherein said plurality of MOS transistor types comprises a low voltage digital transistor type, high voltage digital transistor type, an analog symmetric transistor type and an analog asymmetric transistor type.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The following co-pending application is related and hereby incorporated by reference:
1Serial No.Filing DateInventors(TI-29053)Jun. 11, 1999Chatterjee et al.
Provisional Applications (1)
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Number |
Date |
Country |
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60138727 |
Jun 1999 |
US |
Divisions (1)
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Number |
Date |
Country |
Parent |
09589957 |
Jun 2000 |
US |
Child |
10230559 |
Aug 2002 |
US |