BRIEF DESCRIPTION OF THE DRAWINGS
The above and other features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a flowchart illustrating a method of analyzing the layouts of semiconductor integrated circuit devices according to a first embodiment of the present invention;
FIG. 2 is a flowchart illustrating step S200 of FIG. 1 in detail;
FIGS. 3A to 3C are diagrams illustrating respective steps of FIG. 2;
FIG. 4 is a conceptual diagram illustrating a critical area;
FIG. 5 is a flowchart illustrating step S300 of FIG. 1 in detail;
FIGS. 6A to 6C are diagrams illustrating respective steps of FIG. 5;
FIG. 7 is a flowchart illustrating a method of analyzing the layouts of semiconductor integrated circuit devices according to a second embodiment of the present invention;
FIG. 8 is a flowchart illustrating a method of analyzing the layouts of semiconductor integrated circuit devices according to a third embodiment of the present invention;
FIG. 9 is a conceptual diagram in which a semiconductor integrated circuit device is divided into a plurality of circuit blocks;
FIG. 10 is a flowchart illustrating a system for analyzing the layouts of semiconductor integrated circuit devices according to a first embodiment of the present invention;
FIG. 11 is a flowchart illustrating a system for analyzing the layouts of semiconductor integrated circuit devices according to a second embodiment of the present invention; and
FIG. 12 is a flowchart illustrating a system for analyzing the layouts of semiconductor integrated circuit devices according to a third embodiment of the present invention.