Methods and systems for analyzing layouts of semiconductor integrated circuit devices

Abstract

Disclosed is a method of analyzing layouts of semiconductor integrated circuit devices. The method includes calculating random fault rates, systematic fault rates, parametric fault rates, and areas of a plurality of layouts of interest; calculating area-based fault rates of the plurality of layouts of interest using the random fault rate, systematic fault rate, parametric fault rate, and area; and selecting layouts of interest to be corrected from among the plurality of layouts of interest using the area-based fault rates of the plurality of layouts of interest.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a flowchart illustrating a method of analyzing the layouts of semiconductor integrated circuit devices according to a first embodiment of the present invention;

FIG. 2 is a flowchart illustrating step S200 of FIG. 1 in detail;

FIGS. 3A to 3C are diagrams illustrating respective steps of FIG. 2;

FIG. 4 is a conceptual diagram illustrating a critical area;

FIG. 5 is a flowchart illustrating step S300 of FIG. 1 in detail;

FIGS. 6A to 6C are diagrams illustrating respective steps of FIG. 5;

FIG. 7 is a flowchart illustrating a method of analyzing the layouts of semiconductor integrated circuit devices according to a second embodiment of the present invention;

FIG. 8 is a flowchart illustrating a method of analyzing the layouts of semiconductor integrated circuit devices according to a third embodiment of the present invention;

FIG. 9 is a conceptual diagram in which a semiconductor integrated circuit device is divided into a plurality of circuit blocks;

FIG. 10 is a flowchart illustrating a system for analyzing the layouts of semiconductor integrated circuit devices according to a first embodiment of the present invention;

FIG. 11 is a flowchart illustrating a system for analyzing the layouts of semiconductor integrated circuit devices according to a second embodiment of the present invention; and

FIG. 12 is a flowchart illustrating a system for analyzing the layouts of semiconductor integrated circuit devices according to a third embodiment of the present invention.

Claims

1. A method of analyzing layouts of semiconductor integrated circuit devices, the method comprising: calculating random fault rates, systematic fault rates, parametric fault rates, and areas of a plurality of layouts of interest;calculating area-based fault rates of the plurality of layouts of interest using the random fault rates, the systematic fault rates, the parametric fault rates, and the areas; andselecting layouts of interest to be corrected from among the plurality of layouts of interest using the area-based fault rates.

2. The method of claim 1, wherein calculating the random fault rates comprises: calculating a fault size distribution of fault sizes, and a size of a critical area depending upon the fault sizes for each layer of the layout of interest;calculating layer-based random fault rates using the fault size distributions and the sizes of critical areas; andcalculating the random fault rates of the layouts of interest using the layer-based random fault rates.

3. The method of claim 1, wherein calculating the systematic fault rates comprises: a) determining a plurality of Design Of Experiment (DOE) rule values for a design rule;b) measuring DOE design rule-based fault rates;c) counting numbers of features corresponding to each of the DOE rule values in each of the layouts of interest;d) calculating a systematic fault rate of the design rule using the DOE rule value-based fault rates and the numbers of features;repeatedly performing steps a)-d) for a plurality of design rules used in the layout of interest; andcalculating the systematic fault rate of the layout of interest using a plurality of the calculated systematic fault rates of the design rules.

4. The method of claim 1, wherein calculating the parametric fault rate comprises: a) determining a plurality of DOE rule values for a design rules;b) measuring DOE design rule-based fault rates;c) counting numbers of features corresponding to the each of DOE rule values in each of the layouts of interest;d) calculating a parametric fault rate of the design rule using the DOE rule value-based fault rates and the numbers of features;repeatedly performing steps a)-d) for a plurality of design rules used in the layout of interest; andcalculating the parametric fault rate of the layout of interest using the a plurality of calculated parametric fault rates of the design rules.

5. The method of claim 1, wherein calculating area-based fault rates is performed by dividing sums of the random fault rates, systematic fault rates and parametric fault rates by the areas of the layouts of interest.

6. The method of claim 1, wherein selecting the layouts of interest to be corrected from among the plurality of layouts of interest comprises arranging the area-based fault rates in descending order and selecting the layouts of interest to be corrected based on the order in which an arrangement order of the area-based fault rates are arranged.

7. The method of claim 1, wherein the layouts of interest are cell layouts included in a standard cell library.

8. A standard cell library created using the method of analyzing the layouts of semiconductor integrated circuit devices of claim 1.

9. A mask manufactured using the method of analyzing the layouts of semiconductor integrated circuit devices of claim 1.

10. A semiconductor integrated circuit device mask manufactured using the mask of claim 9.

11. A standard cell list in which area-based fault rates of a plurality of cell layouts included in a standard cell library are arranged in descending order, wherein each of the area-based fault rates of the cell layouts is calculated by dividing a sum of the random fault rate, systematic fault rate and parametric fault rate of each of the cell layouts by an area of the cell layout.

12. A method of analyzing layouts of semiconductor integrated circuit devices, the method comprising: calculating random fault rates, systematic fault rates, and parametric fault rates of a plurality of layouts of interest;calculating total fault rates of the plurality of layouts of interest using the random fault rates, the systematic fault rates and the parametric fault rates;counting usage frequencies of the plurality of layouts of interest within a semiconductor integrated circuit device; andcalculating fault rates which may be generated by the plurality of layouts of interest within a semiconductor integrated circuit device using the total fault rates and the usage frequencies.

13. The method of claim 12, wherein calculating the random fault rates comprises: calculating a fault size distribution of fault sizes, and a size of an critical area depending upon the fault sizes for each layer of the layout of interest;calculating layer-based random fault rates using the fault size distributions and the sizes of critical areas; andcalculating the random fault rates of the layouts of interest using the layer-based random fault rates.

14. The method of claim 12, wherein calculating the systematic fault rates comprises: a) determining a plurality of DOE rule values for a design rule;b) measuring DOE design rule-based fault rates;c) counting numbers of features corresponding to each of the DOE rule values in each of the layouts of interest;d) calculating a systematic fault rate of the design rule using the DOE rule value-based fault rates and the numbers of features;repeatedly performing steps a)-d) for a plurality of design rules used in the layout of interest; andcalculating the systematic fault rate of the layout of interest using a plurality of the calculated systematic fault rates of the design rules.

15. The method of claim 12, wherein calculating the parametric fault rate comprises: a) determining a plurality of DOE rule values for a design rule;b) measuring DOE design rule-based fault rates;c) counting numbers of features corresponding to each of the DOE rule values in each of the layouts of interest;d) calculating a parametric fault rate of the design rule using the DOE rule value-based fault rates and the numbers of features;repeatedly performing steps a)-d) for a plurality of design rules used in the layout of interest; andcalculating the parametric fault rate of the layout of interest using a plurality of the calculated parametric fault rates of the design rules.

16. The method of claim 12, wherein calculating total fault rates comprises summing the random fault rates, systematic fault rates and parametric fault rates of the layouts of interest.

17. The method of claim 12, wherein each of the fault rates which may be generated by the layouts of interest within the semiconductor integrated circuit is calculated by multiplying the total fault rate of the layout of interest and the usage frequency corresponding to the layout of interest.

18. The method of claim 12, wherein the layouts of interest are cell layouts included in a standard cell library.

19. The method of claim 12, further comprising arranging the fault rates which may be generated by the layouts of interest within the semiconductor integrated circuit in descending order and selecting the layouts of interest to be corrected based on the order in which fault rates are arranged.

20. A mask manufactured using the method of analyzing the layouts of semiconductor integrated circuit devices of claim 12.

21. A semiconductor integrated circuit device manufactured using the mask of claim 20.

22. A method of analyzing layouts of semiconductor integrated circuit devices, the method comprising: dividing a semiconductor integrated circuit device into a plurality of circuit blocks;calculating at least one of a random fault rate, a systematic fault rate and a parametric fault rate for each of the circuit blocks; andselecting yield-critical circuit blocks using the calculated random fault rates, systematic fault rates and parametric fault rates of the circuit blocks.

23. The method of claim 22, wherein the plurality of circuit blocks includes one or more memory blocks, one or more functional blocks, and one or more blocks formed of standard cells and/or one or more routing blocks.

24. The method of claim 22, wherein calculating the random fault rates comprises: calculating a fault size distribution of fault sizes, and a size of an critical area depending upon the fault sizes for each layer of the circuit blocks;calculating layer-based random fault rates using the fault size distributions and the sizes of critical areas; andcalculating the random fault rates of the circuit block using the layer-based random fault rates.

25. The method of claim 22, wherein calculating the systematic fault rates comprises: a) determining a plurality of DOE rule values for a design rule;b) measuring DOE design rule-based fault rates;c) counting numbers of features corresponding to each of the DOE rule values in the circuit block;d) calculating a systematic fault rate of the design rule using the DOE rule value-based fault rates and the numbers of features;repeatedly performing steps a)-d) for a plurality of design rules used in the circuit block; andcalculating the systematic fault rate of the circuit block using the calculated systematic fault rates of the design rules.

26. The method of claim 22, wherein calculating the parametric fault rate comprises: a) determining a plurality of DOE rule values for a design rule;b) measuring DOE design rule-based fault rates;c) counting numbers of features corresponding to each of the DOE rule values in each of the circuit block;d) calculating a parametric fault rate of the design rule using the DOE rule value-based fault rates and the numbers of features;repeatedly performing steps a)-d) for a plurality of design rules used in the circuit block; andcalculating the parametric fault rate of the circuit block using the calculated parametric fault rates of the design rules.

27. A system for analyzing layouts of semiconductor integrated circuit devices, the system comprising: a random fault rate calculation unit for calculating random fault rates of a plurality of layouts of interest;a systematic fault rate calculation unit calculating systematic fault rates of the plurality of layouts of interest;a parametric fault rate calculation unit calculating parametric fault rates of the plurality of layouts of interest;an area-based fault rate calculation unit calculating area-based fault rates of the plurality of layouts of interest; anda control unit selecting layouts of interest to be corrected from among the plurality of layouts using the area-based fault rates of the plurality of layouts.

28. A system for analyzing layouts of semiconductor integrated circuit devices, the system comprising: a random fault rate calculation unit calculating random fault rates of a plurality of layouts of interest;a systematic fault rate calculation unit calculating systematic fault rates of the plurality of layouts of interest;a parametric fault rate calculation unit calculating parametric fault rates of the plurality of layouts of interest;a total fault rate calculation unit calculating total fault rates from the random fault rates, systematic fault rates, and parametric fault rates;a counter respectively counting usage frequencies of the layouts of interest within a semiconductor integrated circuit device; anda fault rate calculation unit calculating fault rates which may be generated by the layouts of interest within the semiconductor integrated circuit device using the total fault rates and the frequencies.

29. A system for analyzing layouts of semiconductor integrated circuit devices, the system comprising: a random fault rate calculation unit calculating random fault rates for circuit blocks, wherein a semiconductor integrated circuit device which is divided into a plurality of circuit blocks;a systematic fault rate calculation unit calculating systematic fault rates for the circuit blocks;a parametric fault rate calculation unit calculating parametric fault rates for the circuit blocks; anda control unit selecting yield-critical circuit blocks using the calculated the random fault rates, the systematic fault rates and the parametric fault rates for the circuit blocks.

30. A mask manufactured using the system of analyzing the layouts of semiconductor integrated circuit devices of claim 27.

31. A semiconductor integrated circuit device manufactured using the mask of claim 30.