The present invention relates generally to semiconductor devices and more particularly to methods and systems for forming shallow trench isolation structures in the manufacture of semiconductor devices.
In the area of semiconductor device fabrication, the metal-oxide-semiconductor (MOS) transistor is a basic building block, wherein the transistor can be controlled to operate either in a digital or analog manner. In the fabrication of MOS transistors, source and drain regions are doped opposite that of a body region or well region in a semiconductor substrate. For example, as illustrated in prior art
As transistor devices are scaled down to improve device density, both the width “W” and the channel length “L” dimensions are reduced, giving rise to various fabrication and device performance issues. One problem associated with a reduction in the transistor width “W” is experienced when shallow trench isolation (STI) is employed for device isolation, and that problem is sometimes referred to as the inverse narrow width effect (INWE). As the transistor width is reduced the transistor drive current per unit width changes due to the edge effects that now play an appreciable role in transistor behavior. The gate dielectric thickness, its dielectric constant, and the channel orientation are different at the edges than at the planar center of the channel. The dopant concentration at the edges is different at than the center due to dopant segregation and STI stress induced diffusion at the interface. There is also the impact of STI and liner stress on the mobility near the edge of the channels. The STI edge may not be completely planar and may have a gate wrap around (more gate control) or less gate control depending upon the step height (difference between the top of the oxide over field and the top of the active regions). All these factors alter (raise or lower) threshold voltages of the narrow width device resulting in either reduction or increase in drive current per unit width. When the threshold voltage increases for narrow width devices and the drive current per unit width is reduced it results in weaker SRAM transistors which result in slower memory for example as well as functional problems for given SRAM designs. In such cases there is a need to improve the narrow width effects by mitigating the narrow width effects.
Therefore there is a need in the art for improved STI processes and techniques that reduce or alter the impact of the INWE in order to reduce or mitigate the device performance problems associated therewith.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The invention provides methods for forming isolation structures and STI trenches in a semiconductor device, which may be carried out in a variety of semiconductor manufacturing processes. One embodiment of the invention relates to a method of forming a semiconductor device having isolation structures. In this method, trench regions are formed within a semiconductor body, and then surfaces of the trench regions are nitrided. Then the nitrided surfaces are subjected to a condition that limits nitrogen desorption from the nitrided surfaces. The nitrided surfaces of the trench regions are then oxidized to form nitrogen containing liners, after which the isolation trench is filled with a dielectric material.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
The present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout. The invention relates to methods for forming isolation structures and trenches in semiconductor devices, in which the negative impacts of the INWE are eliminated or substantially mitigated without the addition of extra mask steps. In addition, the method according to one exemplary aspect of the invention advantageously operates to improve a balance or minimize an imbalance of the threshold voltage performance of NMOS and PMOS transistors.
In order to fully appreciate the various aspects of the present invention, a brief description of a conventional STI fabrication process as appreciated by the inventors of the present invention will be discussed. After a discussion thereof, the various aspects of the present invention will be disclosed and more fully appreciated.
In the fabrication of semiconductor devices, isolation structures are formed between active areas in which electrical devices such as transistors, memory cells, or the like, are to be formed. The isolation structures, in this case shallow trench isolation (STI) structures, are typically formed during initial processing of a semiconductor substrate, prior to the formation of such electrical devices.
STI isolation techniques involve the formation of shallow trenches in the isolation areas or regions of a semiconductor wafer, which are subsequently filled with dielectric material such as silicon dioxide (SiO2) to provide electrical isolation between devices subsequently formed in the active regions on either side of the filled trenches. A mask, such as a resist mask, is formed over the substrate surface and patterned to expose only the isolation regions, with the prospective active device regions covered. An anisotropic (e.g., “dry”) etch is then performed to form a trench through the substrate. Once the trench is etched, dielectric material is deposited to fill the trench with oxide. Thereafter, the device is commonly planarized using a chemical mechanical polishing (CMP) process.
An example of a conventional STI process is illustrated in prior art
Once the trench 124 and the liner 126 are formed, a dielectric material 128 is deposited in prior art
The inventors of the present invention note that the conventionally formed STI structure 128 can lead to inverse width effects if the device 112 has a relatively small width dimension. These inverse width effects can degrade drive current, undesirably alter threshold voltages, and the like.
Referring now to
Beginning at block 902, a hard mask layer is formed over a silicon semiconductor substrate or body of a semiconductor device. A relatively thin pad oxide layer may be formed on the semiconductor substrate prior to formation of the hard mask layer by thermally growing oxide. The hard mask is comprised of a suitable material, such as nitride (Si3N4) and is deposited, for example, by a low pressure chemical vapor deposition (LPCVD) or other suitable deposition process. The hard mask layer mitigates damage to active regions of the device during formation of isolation regions.
Continuing at block 904, a resist mask layer is formed over the device and on the hard mask layer that covers the active regions and exposes isolation regions. A photoresist material is deposited on the hard mask layer and patterned to expose the hard mask layer within the isolation regions and yet remain and cover the hard mask layer within the active regions.
The hard mask layer is then patterned using a suitable etch/patterning process and the resist mask layer as a mask at block 906 to expose underlying silicon of the isolation regions. The resist layer may then be removed by an ashing process. Subsequently, a trench formation process is performed at block 908 that etches the exposed portions of the silicon substrate to a selected depth, thereby forming trench regions. The etch process employed is typically selective to the material employed in the mask layer and etches into the semiconductor substrate within the exposed isolation regions so as to form the trench region having sidewalls, and a bottom. The width of the insulation trench is associated with the isolation opening(s) in the mask layer.
A number of suitable etch processes can be employed to form the trench regions at block 908. For example, a dry etch can be employed, which works well with hard mask layers. Additionally, reactive ion etching (RIE) can be employed. For example, a single or multi-step RIE etch process may be performed which removes material in the exposed isolation regions. Other suitable etch processes can also be employed.
At block 910, a nitridation process is performed that nitrides a surface of the sidewalls and bottom of the trench region. The nitridation doesn't necessarily form a nitride compound. A number of nitridation processes can be employed, such as plasma (non-thermal) nitridation. As an example, a suitable plasma nitridation process is performed using pulsed RF plasma with approximately 30-60% duty pulse with N2 gas flow of approximately 100-700 sccm, pressure of approximately 5-30 mTorr for approximately 15-60 seconds.
Because the plasma nitridation process may be intense, it can form a plasma damaged layer on the top of the nitrided surface. The plasma damaged layer is thermally unstable. Because of this thermal instability, air can reduce this layer at room temperature, which leads to nitrogen loss, absent countermeasures. In one embodiment (see
In order to combat this nitrogen loss, the nitrided surfaces are subjected to a condition to prevent the nitrogen atoms from desorbing from these nitrided surfaces at block 912. Thus, the nitrogen atoms that escape from the nitrided surface can be minimized or limited. The present invention extends to any condition by which the escape of nitrogen atoms from the nitrided surface could be minimized or limited, including but not limited to: an environmental condition, a voltage bias condition, a magnetic condition, a chemistry condition, or some other mechanism.
In one embodiment, the condition is an environmental condition such as a low O2 environment, a high-vacuum environment, a low-vacuum environment, or a high N2 environment, or some other environmental condition that prevents the nitrogen atoms from escaping from the nitrided surface.
In various embodiments, this environmental condition can be achieved by using a “cluster” tool (see e.g.,
After the condition is applied, an oxidation process is performed at block 914 that forms a nitrogen containing liner, such as nitrous oxide (N2O), nitric oxide, or combination thereof liner. The oxidation process can be a thermal oxidation process and/or another suitable oxidation process. The concentration of nitrogen can vary throughout the nitride containing oxide liner layer. However, a nitrogen profile having a relatively higher nitrogen concentration near an interface between the silicon substrate and the liner can increasingly mitigate problems resulting from inverse width effects as one of benefits of the nitrided STI liner. As an example, N2O oxidation could be done at approximately 1000-1150° C. at a pressure of 100-400 Torr for approximately 30-60 seconds under pure N2O flow of approximately 9500 sccm.
It is noted that the inventors of the present invention contemplate alternate aspects of the invention that include other processes for forming nitrous oxide, nitric oxide, and other liners containing nitrogen. It is also noted the nitridation performed at block 910 prior to formation of the nitrogen containing liner at block 914 facilitates increasing the nitrogen composition at the silicon/liner interface.
Subsequently, an anneal is performed at block 916 after the formation of the nitrogen containing liner (e.g., nitrous oxide). The anneal serves to repair damage and/or mitigate uniformities within the trench region and the nitrogen containing liner layer.
At 918, the trench is filled with dielectric material such as SiO2 or other electrically isolating material so as to provide electrical isolation between active regions on either side of the isolation trench. The trench filling operation at 918 may comprise forming or depositing dielectric material over the device to cover the hard mask layer in the active regions and to fill the trenches in the isolation regions thereof. The trench fill material may be deposited at 918 using any appropriate deposition techniques, for example, such as high density plasma (HDP) oxide deposition, low pressure chemical vapor deposition (LPCVD) employing a tetraethylorthosilicate (TEOS) gas, or plasma enhanced chemical vapor deposition (PECVD) of silicon dioxide from TEOS and oxygen mixtures (PETEOS).
The device is then planarized at 920 to expose a portion of the hard mask layer in the active regions, leaving a generally planar upper surface with portions of the nitride layer and a remaining portion of the fill material in the trench exposed. The remaining hard mask material is stripped or removed at 922, for example, using a wet etch process selective so as to remove hard mask material and to stop on or before the silicon substrate (e.g., a pad oxide layer can be employed) without damaging the underlying silicon or other semiconductor material in the active regions of the device. The isolation method 900 then ends. Thereafter, transistors, memory cells, and/or other electrical devices may be formed in the active regions using semiconductor processing techniques as are known.
The presence of nitrogen in the liner layer serves a number of purposes. The threshold voltages for relatively narrow width NMOS devices is generally reduced by the presence of nitrogen in the liner layer and the threshold voltages for relatively narrow PMOS devices is generally increased (decreased in magnitude) by the presence of nitrogen in the liner layer. Narrow width devices are typically defined as devices whose width is small enough that inverse width effects substantially deteriorate operation of the devices using conventional shallow trench isolation processing. Generally, narrow width devices of interest are under 200 nm in width.
The above alterations of threshold voltages facilitate improving drive current for transistor devices. For example, as a consequence, SRAM drive current over the SRAM load is increased thereby increasing the SRAM beta ration. The presence of nitrogen also reduces undesired diffusion of implanted source/drain dopants toward the surfaces of the active regions thereby preventing/mitigating the rise of threshold voltage for relatively narrow width devices.
Referring now to
In
Thereafter, in
Continuing with respect to
A nitridation process is then performed that nitrides surfaces of the sidewalls and bottom of the trench regions 1014. Typically, a plasma nitridation process is employed. The nitridation process parameters, including source materials and duration, can be adjusted to obtain a desired nitridation of the surfaces.
After the nitrided surfaces 1016 are formed, they are subjected to a condition to prevent the nitrogen atoms from desorbing from these nitrided surfaces in
Thereafter, an oxidation process is performed that forms a nitrogen containing liner 1020 on the sidewalls and bottom of the trench regions 1014 as shown in
The trench regions 1014 are then filled in with electrically isolating, dielectric material 1022 via a deposition process as shown in
Continuing with
Thereafter, transistors, memory cells, and/or other electrical devices (not shown) may be formed in the active regions using semiconductor processing techniques as are known.
Thus, absent the application of the condition as set forth above, the nitrogen concentration of the liner will decrease as a function of time as shown by curve 1502. Note that the nitrogen concentration 1502 is representative of one depth or “slice” within the liner, and it will be appreciated that the nitrogen profile could vary over the depth of the liner and this “slice” of the profile is exemplary in nature.
Because the nitriding layer has advantageous properties and improves device characteristics and performance, it is desirable to keep the nitrogen concentration at relatively high levels. Further, as with any process step, it is desirable to retain precise control of the nitrogen concentration and thickness of the liner layer. Therefore, by applying the condition these undesirable effects may be limited or eliminated altogether.
Referring now to
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Although the invention has been illustrated and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.”