The present disclosure relates to power conversion, and more particularly, to methods, apparatuses, integrated circuits, and printed circuit boards for power conversion with reduced parasitic losses.
Many electronic products, particularly mobile computing and/or communication products and components (e.g., notebook computers, ultra-book computers, tablet devices, LCD and LED displays), require multiple voltage levels. For example, power amplifiers for radio frequency transmitters may require relatively high voltages (e.g., 12 volts (V) or more), and logic circuitry may require a low voltage level (e.g., 1-2 V). Some other circuitry may require an intermediate voltage level (e.g., 5-10 V). Power converters are often used to generate a lower or higher voltage from a common power source, such as a battery, in order to meet the power requirements of different components in electronic products.
Embodiments of the present disclosure may provide methods, apparatuses, integrated circuits, and printed circuit boards for power conversion with reduced parasitic losses.
It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not restrictive of the invention, as claimed.
The following disclosure provides different exemplary embodiments, or examples, for implementing different features of the provided subject matter. Specific simplified examples of components and arrangements are described below to explain the present disclosure. These embodiments are examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
The terms used in this specification generally have their ordinary meanings in the art and in the specific context where each term is used. The use of examples in this specification, including examples of any terms discussed herein, is illustrative only, and in no way limits the scope and meaning of the disclosure or of any exemplified term. Likewise, the present disclosure is not limited to various embodiments given in this specification.
Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
Spatially relative terms, such as “beneath,” “below,” “lower,” “bottom,” “above,” “upper”, “top,” “toward,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
In this disclosure, the term “coupled” may also be termed as “electrically coupled”, and the term “connected” may be termed as “electrically connected”. “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other.
Power converters can receive, deliver or operate with high current in one or more of the current paths. The power delivery path and operation at high current can be susceptible to parasitic losses that negatively impact performance. Parasitic losses may be described as the product of I2 and R, where “I” is current and “R” is resistance. As the current increases, the power loss becomes more pronounced. For example, the power delivery path and the high current of certain buck converters can reduce their power conversion efficiency due to the parasitic losses. Additional constraints may further exacerbate unwanted parasitic losses. For example, die space may be limited, prompting signals to be fanned out on a printed circuit board (PCB) and be routed as needed.
For example, in some applications (e.g., servers, routers, etc.), optical cables may be interfaced using small form-factor pluggable (SFP) modules (e.g., optical transceivers, quad SFPs (QSFPs), octal SFPs (OSFPs), bidirectional QSFP28 (BIDI QSFP28), QSFP double density (QSFP-DD), applications where transmission rates are greater than 200 Gigabits per second (G), 400 G, greater than 200 G, etc.). These modules require high current (e.g., 20 ampere (A)) and low voltage (e.g., 0.5 volts (V)) outputs to operate at high performance. However, high current, low voltage paths are very sensitive to parasitic losses in a PCB. Moreover, SFP modules use narrow and long PCBs, which may further exacerbate unwanted parasitic losses in the PCB.
Typical SFP modules may suffer from parasitic losses. For example, typical SFP modules use a single integrated circuit coupled to one or more inductors to convert an input voltage (e.g., from 3.3 V to 0.5 V at 20 A) to an output voltage for a coupled main signal processing application-specific integrated circuit (ASIC). One or more terminals of the single integrated circuit is coupled to one or more inductors which is further coupled to the main signal processing ASIC. Typically, in order to increase current provided by the single integrated circuit and the one or more inductors to the ASIC, the terminals are placed on multiple sides of the integrated circuit. However, using multiple terminals in close proximity to transfer current to inductors from a single integrated circuit results in so-called “current crowding” along the current path. Current crowding may increase current density that causes increased parasitic losses in a PCB.
Disclosed embodiments may, among other things, reduce such parasitic losses by routing current from an input voltage to one or more integrated circuits, where each integrated circuit includes buck converter circuitry. For example, the one or more integrated circuits may be positioned adjacent to each other along a width of a PCB such that current crowding on each integrated circuit is reduced or eliminated. In some embodiments, each integrated circuit may be coupled to one or more inductors by corresponding terminals. For example, each terminal may be positioned on a same or common side of each integrated circuit such that each inductor of the one or more inductors are adjacent to each other on the same or common side of the one or more integrated circuits. Disclosed embodiments may reduce or eliminate current crowding on any of the one or more integrated circuits by routing current from the input voltage to the one or more terminals across a width of the PCB, thereby reducing or eliminating parasitic losses and increasing efficiency in the PCB.
Disclosed embodiments may include designs that reduce the inductor requirements for buck converters. For example, embodiments may include one or more charge pumps either part of each integrated circuit, or in separate integrated circuit(s), to reduce input voltage provided to each buck converter.
Because this arrangement reduces the inductor requirements for the buck converter (e.g., each inductor may have a dimension of 2.5 mm×2.0 mm×1.2 mm), it may permit embodiments to use chip inductors for the buck converter even with relatively high input voltage (e.g., 3.3 V). For example, each integrated circuit may be coupled to a corresponding charge pump such that each charge pump may step down the input voltage before it is provided to the corresponding buck converter. Allowing the buck converter to operate using a stepped-down voltage may reduce the demands on its associated inductor such that a chip inductor may be used instead of a larger inductor that takes up additional space.
While embodiments of the present disclosure may address these challenges and provide these benefits, the stated problems and features are intended to be examples and not limit the claims or scope of this disclosure. Indeed, the disclosed embodiments may address challenges and provide benefits not explicitly enumerated.
It should be understood that in some embodiments, repeat reference numerals and/or letters in various figures of the present disclosure relate to one another and indicate that the figures relate to one another. In some other embodiments, this repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
It should be understood that in some embodiments, repeat reference numerals and/or letters in various figures of the present disclosure relate to one another and indicate that the figures relate to one another. In some other embodiments, this repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
As shown in
In some embodiments, the layout of PCB 100 may be designed to reduce or eliminate parasitic losses along certain conductive paths of PCB 100. For example, the field effect transistor (FET) formed with the terminals between a buck converter and an inductor may be particularly susceptible to the parasitic losses caused by current crowding on the integrated circuit of the buck converter. Disclosed embodiments may, among other things, reduce such unwanted parasitic losses by routing current from an input voltage to integrated circuit IC1 and to integrated circuit IC2. Integrated circuits IC1 and IC2 may be positioned adjacent to each other along a width of PCB 100 such that current crowding on integrated circuits IC1 and IC2 in reduced or eliminated.
Disclosed embodiments may advantageously reduce parasitic losses by optimizing a critical path of the integrated circuit (IC) at the cost of a non-critical path. A buck converter operating at a low duty cycle (e.g., <50%) is more dependent on the low-side FET current path (e.g., ML1) for better efficiency than the high-side current path (e.g., MH1). For example, disclosed embodiments may optimize the critical path GND-ML1-LX of an integrated circuit (e.g., integrated circuits IC1, IC2, or ICN) from a switch to a terminal (e.g., terminals LX1, LX2, LX3, or LX4) on one side of the integrated circuit at the cost of the non-critical path LX-MH1-VX at another side of the integrated circuit from a switch to a charge pump (e.g., charge pumps CP1 or CP2). Disclosed embodiments may reduce parasitic losses by using a lead frame to bridge the distance between the critical path and the non-critical path. For example, the charge pump and the integrated circuit may use the lead frame.
As shown in
Inductors L1, L2, L3, and L4 may be chip inductors that may feature a small package and may be used for various applications, including power conversion and high-frequency circuitry. A chip inductor may be an inductor that comes in the form factor of a chip for use in an integrated circuit of an electronic device. Chip inductors may be used in power converters, RF transceivers, computers, and other electronic devices. An example chip inductor may include a ferrite core with a wire winding or may have multiple layers of wires. Chip inductors may offer the benefits of conserving voltage and may be used to form filter circuits and resonant circuits. As compared with conventional discrete inductors, chip inductors may be more compact and may weigh less.
While,
As shown in
Charge pump CP1 may be arranged between input voltages VIN-1 and VIN-2 and integrated circuit IC1. Similarly, PCB 100 may include charge pump CP2 to step down input voltages VIN-3 and VIN-4, where charge pump CP2 may be a dual phase charge pump formed by integrated circuit IC2 in conjunction with capacitors C3 and C4, where each phase is divided by two. Charge pump CP2 may be arranged between input voltages VIN-3 and VIN-4 and integrated circuit IC2.
Integrated circuit IC1 in conjunction with inductors L1 and L2 may form a first buck regulator. Similarly, integrated circuit IC2 in conjunction with inductors L3 and L4 may form a second buck regulator. Integrated circuit IC1 and integrated circuit IC2 may include power switches for the first and second buck regulators, respectively.
Charge pump CP1 may step down input voltages VIN-1 and VIN-2 before they are provided to integrated circuit IC1. Similarly, charge pump CP2 may step down input voltages VIN-3 and VIN-4 before they are provided to integrated circuit IC2. A lower input voltage to the buck converter may reduce the demands on inductors L1, L2, L3, and L4. In some embodiments, inductors L1, L2, L3, and L4 may therefore be implemented by chip inductors instead of larger inductors that take up additional space.
In some embodiments, current may be transferred to terminals (e.g., terminals GND1 or GND2) on an integrated circuit (e.g., integrated circuit IC1) from a corresponding charge pump (e.g., charge pump CP1) non-simultaneously. For example, current may transfer from charge pump CP1 to terminal GND1 at a point in time without any current transferring from charge pump CP1 to terminal GND2. This operation may further reduce or eliminate negative parasitic losses from current crowding on any terminals or inductors, thereby increasing power conversion efficiency. This non-simultaneous current transfer may similarly occur with terminals GND2, GND3, or GND4.
While the integrated circuits (e.g., integrated circuits IC1, IC2, or ICN) include power switches that connect to capacitors and inductors to form charge pumps and buck regulators that offer some advantages and are depicted in
During power conversion, currents may flow from charge pump C1 to integrated circuit IC1 through conductive lines 111 and 113 and currents may flow from charge pump C2 to integrated circuit IC2 through conductive lines 112 and 114. While other conductive lines and terminals are depicted, but not labelled, in
While disclosed embodiments have described power conversion in the direction from the charge pump to the buck converter, it should be understood that disclosed embodiments are applicable to power conversion in the opposite direction as well (e.g., from the buck converter to the charge pump, wherein a buck converter run backwards is referred to as a boost converter).
While disclosed embodiments have been described with respect to SFP modules, it should be understood that disclosed embodiments are applicable to other applications as well, such as, e.g., any high current, low output voltage applications where the total available width or area of a PCB is limited (though the disclosed embodiments are not limited to such applications).
It should be understood that in some embodiments, repeat reference numerals and/or letters in various figures of the present disclosure relate to one another and indicate that the figures relate to one another. In some other embodiments, this repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
It should be understood that in some embodiments, repeat reference numerals and/or letters in various figures of the present disclosure relate to one another and indicate that the figures relate to one another. In some other embodiments, this repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
It should be understood that in some embodiments, repeat reference numerals and/or letters in various figures of the present disclosure relate to one another and indicate that the figures relate to one another. In some other embodiments, this repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
As shown in
It should be understood that in some embodiments, repeat reference numerals and/or letters in various figures of the present disclosure relate to one another and indicate that the figures relate to one another. In some other embodiments, this repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
It should be understood that in some embodiments, repeat reference numerals and/or letters in various figures of the present disclosure relate to one another and indicate that the figures relate to one another. In some other embodiments, this repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
It should be understood that in some embodiments, repeat reference numerals and/or letters in various figures of the present disclosure relate to one another and indicate that the figures relate to one another. In some other embodiments, this repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
It should be understood that in some embodiments, repeat reference numerals and/or letters in various figures of the present disclosure relate to one another and indicate that the figures relate to one another. In some other embodiments, this repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
It should be understood that in some embodiments, repeat reference numerals and/or letters in various figures of the present disclosure relate to one another and indicate that the figures relate to one another. In some other embodiments, this repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
It should be understood that in some embodiments, repeat reference numerals and/or letters in various figures of the present disclosure relate to one another and indicate that the figures relate to one another. In some other embodiments, this repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
It should be understood that in some embodiments, repeat reference numerals and/or letters in various figures of the present disclosure relate to one another and indicate that the figures relate to one another. In some other embodiments, this repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
In the foregoing specification, embodiments have been described with reference to numerous specific details that can vary from implementation to implementation. Certain adaptations and modifications of the described embodiments can be made. Other embodiments can be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. It is also intended that the sequence of steps shown in figures are only for illustrative purposes and are not intended to be limited to any particular sequence of steps. As such, those skilled in the art can appreciate that these steps can be performed in a different order while implementing the same method.
It is appreciated that certain features of the specification, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the specification, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub-combination or as suitable in any other described embodiments of the specification. Certain features described in the context of various embodiments are not to be considered essential features of those embodiments unless the embodiment is inoperative without those elements.
The embodiments may further be described using the following clauses:
1. A printed circuit board (PCB) for power conversion, the PCB comprising:
2. A printed circuit board (PCB) for power conversion, the PCB comprising:
3. The PCB of clause 2, wherein each integrated circuit of the plurality of integrated circuits is coupled to each inductor of the plurality of inductors by a corresponding terminal.
4. The PCB of clause 3, wherein each corresponding terminal is positioned on a common side of each integrated circuit of the plurality of integrated circuits.
5. The PCB of clause 2, wherein the plurality of integrated circuits are adjacent to each other.
6. The PCB of clause 2, wherein the plurality of inductors are adjacent to each other on a common side of the plurality of integrated circuits.
7. The PCB of clause 2, wherein each integrated circuit of the plurality of integrated circuits is coupled to a corresponding charge pump.
8. The PCB of clause 7, wherein each corresponding charge pump comprises one or more capacitors.
9. An apparatus comprising the PCB of any one of clauses 1-8.
10. A printed circuit board (PCB) for power conversion comprising:
11. The PCB of clause 10, wherein:
12. The PCB of clause 11, wherein each the first terminal, the second terminal, the third terminal, and the fourth terminal are positioned on a common side of each integrated circuit of the plurality of integrated circuits.
13. The PCB of clause 10, wherein the first inductor, the second inductor, the third inductor, and the fourth inductor are adjacent to each other on a common side of the first integrated circuit and the second integrated circuit.
14. The PCB of clause 10, wherein the first integrated circuit is coupled to a first charge pump and the second integrated circuit is coupled to a second charge pump.
15. The PCB of clause 14, wherein the first charge pump and the second charge pump each comprises one or more capacitors.
16. An apparatus comprising the PCB of any one of clauses 10-15.
This application is a continuation of International Patent Application No. PCT/US2023/064783 filed Mar. 21, 2023 and entitled “METHODS, APPARATUSES, INTEGRATED CIRCUITS, AND PRINTED CIRCUIT BOARDS FOR POWER CONVERSION WITH REDUCED PARASITICS,” which claims priority to and the benefit of U.S. Provisional Patent Application No. 63/321,930 filed Mar. 21, 2022 and entitled “METHODS, APPARATUSES, INTEGRATED CIRCUITS, AND PRINTED CIRCUIT BOARDS FOR POWER CONVERSION WITH REDUCED PARASITICS,” all of which are hereby incorporated by reference in their entirety.
Number | Date | Country | |
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63321930 | Mar 2022 | US |
Number | Date | Country | |
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Parent | PCT/US2023/064783 | Mar 2023 | WO |
Child | 18893873 | US |