Claims
- 1. A method for providing a value of a physical parameter relating to conductors and dielectric layers in an integrated circuit structure fabricated under a manufacturing process, said method comprising:fabricating using said manufacturing process one or more test structures, each of said test structures being a physical model of said integrated circuit structure designed to allow an independent measurement of a quantity parametrically dependent upon said physical parameter; and deriving said physical parameter from said independent measurements of said quantity using an electric field solver.
- 2. A method as in claim 1, wherein said method determines a value of an interconnect process parameter, wherein said quantity is a value of an electrical property; and wherein said deriving step comprises:measuring in each of said test structures said value of said electrical property; using said electric field solver to predict said value of said electrical property based on successive approximated values of said interconnect process parameter; and selecting one of said successive approximated values as said value of said interconnect process parameter, when said selected value substantially approximates said measured value of said electrical property.
- 3. A method as in claim 1, wherein said method determines a value of an interconnect process parameter relating to conductor lines of an interconnect process, wherein said conductor lines each has non-rectangular dimensions characterized by a plurality of dimensional parameters, and wherein said deriving step comprises:determining the values of said plurality of dimensional parameters using one or more of said independent measurements; and determining a value for said interconnect process parameter using said electric field solver, said field solver including in its physical model said values of said plurality of dimensional parameters.
- 4. A method as in claim 3, wherein said conductors comprises a plurality of materials forming different portions of said conductors, each portion having a set of dimensions resulting from manufacturing processing, said values of said plurality of dimensional parameters includes dimensions of each portion of said conductors.
CROSS-REFERENCE TO RELATED APPLICATIONS
The present Application is a divisional application of U.S. Patent Application, entitled “Methods for Determining On-Chip Interconnect Process Parameters,” Ser. No. 08/937,393, filed Sep. 25, 1997 now U.S. Pat. No. 6,057,171, assigned to Frequency Technology, Inc., which is also the Assignee of the present Application.
US Referenced Citations (11)
Foreign Referenced Citations (2)
Number |
Date |
Country |
09 186213 |
Jul 1997 |
JP |
09 246269 |
Sep 1997 |
JP |