Claims
- 1. A method of producing a monolithic integrated chip with built-in transient voltage suppression, the method comprising:
providing a monolithic, epitaxially-grown substrate assembly, wherein the substrate assembly includes:
a semi-insulating substrate; an N+ sub-collector layer; an N-type collector layer; a P-type base layer; and an N-type emitter layer; removing selected portions of the N-type emitter layer to isolate transistors and steering diodes, where at least a remaining portion of the N-type emitter layer is used to fabricate emitters for transistors; removing selected portions of the P-type base layer to isolate transistors and steering diodes, where at least a remaining portion of the P-type base layer is used to fabricate bases for transistors and anodes for steering diodes; removing selected portions of the N-type collector layer to isolate transistors and steering diodes, where at least a remaining portion of the N-type collector layer is used to fabricate collectors for transistors and cathodes for steering diodes; isolating regions in the N+ sub-collector layer such that transistors and steering diodes are electrically isolated; forming an insulating layer on selected portions the substrate assembly; and forming electrical connections to the transistors and steering diodes.
- 2. The method as defined in claim 1, wherein the removing selected portions of the N-type emitter layer further comprises removing all of the N-type emitter layer above a portion of a base layer that is used to form an anode of a steering diode.
- 3. The method as defined in claim 1, wherein the isolating regions comprises ion-implanting isolation regions in the N+ sub-collector layer.
- 4. The method as defined in claim 1, wherein the monolithic epitaxially-grown substrate assembly comprises at least one of gallium arsenide (GaAs), indium gallium phosphide (InGaP), gallium nitride (GaN), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), indium gallium arsenide (InGaAs), indium gallium aluminum phosphide (InGaAlP), indium gallium arsenide phosphide (InGaAsP), indium gallium nitride (InGaN), and aluminum gallium nitride (AlGaN).
- 5. The method as defined in claim 1, wherein the monolithic epitaxially-grown substrate assembly comprises at least one of gallium arsenide (GaAs) and indium phosphide (InP).
- 6. The method as defined in claim 1, wherein the monolithic epitaxially-grown substrate assembly comprises at least one of silicon carbide (SiC) and silicon germanium (SiGe).
- 7. A method of producing a monolithic integrated chip with built-in transient voltage suppression, the method comprising:
providing a monolithic, epitaxially-grown substrate assembly, wherein the substrate assembly includes:
a semi-insulating substrate; an N+ sub-collector layer; an N-type collector layer; a P-type base layer; and an N-type emitter layer; removing selected portions of the N-type emitter layer to isolate transistors, steering diodes, and breakdown diodes, where at least a remaining portion of the N-type emitter layer is used to fabricate emitters for transistors and cathodes for breakdown diodes; removing selected portions of the P-type base layer to isolate transistors, steering diodes, and breakdown diodes, where at least a remaining portion of the P-type base layer is used to fabricate bases for transistors, anodes for steering diodes, and anodes for breakdown diodes; removing selected portions of the N-type collector layer to isolate transistors, steering diodes, and breakdown diodes, where at least a remaining portion of the N-type collector layer is used to fabricate collectors for transistors and cathodes for steering diodes; isolating regions into the N+ sub-collector layer such that transistors, steering diodes, and breakdown diodes are electrically isolated; forming an insulating layer on selected portions the substrate assembly; and forming electrical connections to the transistors, steering diodes, and breakdown diodes.
- 8. The method as defined in claim 7, wherein the removing selected portions of the N-type emitter layer further comprises removing all of the N-type emitter layer above a portion of a base layer that is used to form an anode of a steering diode.
- 9. The method as defined in claim 7, wherein the monolithic, epitaxially-grown substrate assembly comprises at least one of gallium arsenide (GaAs), indium gallium phosphide (InGaP), gallium nitride (GaN), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), indium gallium arsenide (InGaAs), indium gallium aluminum phosphide (InGaAlP), indium gallium arsenide phosphide (InGaAsP), indium gallium nitride (InGaN), and aluminum gallium nitride (AlGaN).
- 10. The method as defined in claim 7, wherein the monolithic, epitaxially-grown substrate assembly comprises at least one of gallium arsenide (GaAs) and indium phosphide (InP).
- 11. The method as defined in claim 7, wherein the monolithic, epitaxially-grown substrate assembly comprises at least one of silicon carbide (SiC) and silicon germanium (SiGe).
- 12. A method of producing a monolithic integrated chip with built-in transient voltage suppression, the method comprising:
providing a monolithic, epitaxially-grown substrate assembly, wherein the substrate assembly includes:
a semi-insulating substrate; a P+ sub-collector layer; a P-type collector layer; an N-type base layer; and a P-type emitter layer; removing selected portions of the P-type emitter layer to isolate transistors and steering diodes, where at least a remaining portion of the P-type emitter layer is used to fabricate emitters for transistors; removing selected portions of the N-type base layer to isolate transistors and steering diodes, where at least a remaining portion of the N-type base layer is used to fabricate bases for transistors and anodes for steering diodes; removing selected portions of the P-type collector layer to isolate transistors and steering diodes, where at least a remaining portion of the P-type collector layer is used to fabricate collectors for transistors and cathodes for steering diodes; isolating regions into the P+ sub-collector layer to isolate transistors and steering diodes; forming an insulating layer on selected portions the substrate assembly; and forming electrical connections to the transistors and steering diodes.
- 13. The method as defined in claim 12, wherein the monolithic epitaxially-grown substrate assembly comprises at least one of gallium arsenide (GaAs), indium gallium phosphide (InGaP), gallium nitride (GaN), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), indium gallium arsenide (InGaAs), indium gallium aluminum phosphide (InGaAlP), indium gallium arsenide phosphide (InGaAsP), indium gallium nitride (InGaN), and aluminum gallium nitride (AlGaN).
- 14. The method as defined in claim 12, wherein the monolithic epitaxially-grown substrate assembly comprises at least one of gallium arsenide (GaAs) and indium phosphide (InP).
- 15. The method as defined in claim 12, wherein the monolithic epitaxially-grown substrate assembly comprises at least one of silicon carbide (SiC) and silicon germanium (SiGe).
- 16. A method of producing a monolithic integrated chip with built-in transient voltage suppression, the method comprising:
providing a monolithic, epitaxially-grown substrate, wherein the substrate assembly includes:
a semi-insulating substrate; an N+ sub-collector layer; an N-type collector layer; a P-type base layer; and an N-type emitter layer; forming a transistor by:
removing a first portion of the N-type emitter layer, a first portion of the P-type base layer, and a first portion of the N-type collector layer from around a second portion of the N-type emitter layer, a second portion of the P-type base layer, and a second portion of the N-type collector layer; and isolating a first portion of the N+ sub-collector layer by ion implantation, where the ion-implanted first portion of the N+ sub-collector layer isolates a second portion of the N+ sub-collector layer from at least a third portion of the N+ sub-collector layer; forming a steering diode by:
removing a third portion of the N-type emitter layer, where the removed third portion of the N-type emitter layer removes substantially all of a portion of the N-type emitter layer above a third portion and a fourth portion of the P-type base layer; removing the third portion of the P-type base layer and a third portion of the N-type collector layer from around the fourth portion of the P-type base layer and a fourth portion of the N-type collector layer; and using the fourth portion of the P-type base layer and the fourth portion of the N-type collector layer as an anode and a cathode, respectively, of the steering diode; and, coupling at least two steering diodes on the substrate assembly to protect a transistor on the substrate assembly from an undesired voltage transient.
- 17. The method as defined in claim 16, further comprising forming a breakdown diode from a transistor by using a base of the transistor as an anode of the breakdown diode and an emitter of the transistor as a cathode of the breakdown diode.
- 18. The method as defined in claim 16, further comprising forming an electrical connection between the breakdown diode and at least one of the two steering diodes through a metallization layer.
- 19. The method as defined in claim 16, where the monolithic, epitaxially-grown substrate assembly comprises at least one of gallium arsenide (GaAs), indium gallium phosphide (InGaP), gallium nitride (GaN), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), indium gallium arsenide (InGaAs), indium gallium aluminum phosphide (InGaAlP), indium gallium arsenide phosphide (InGaAsP), indium gallium nitride (InGaN), and aluminum gallium nitride (AlGaN).
- 20. The method as defined in claim 16, where the monolithic, epitaxially-grown substrate assembly comprises at least one of gallium arsenide (GaAs) and indium phosphide (InP).
- 21. The method as defined in claim 16, where the monolithic, epitaxially-grown substrate assembly comprises at least one of silicon carbide (SiC) and silicon germanium (SiGe).
- 22. The method as defined in claim 16, where the removing is an etching process.
- 23. A method of using pre-grown layers in a monolithic substrate assembly made from a compound semiconductor to form a transient voltage protection circuit, the method comprising:
fabricating collector regions for transistors and cathode regions for steering diodes from an N-type collector layer; fabricating base regions for transistors and anode regions for steering diodes from a P-type base layer; fabricating an emitter region for a transistor and a cathode region for a breakdown diode from an N-type emitter layer; coupling an anode of a first steering diode to a data line that is coupled to a transistor; coupling a cathode of the first steering diode to a first reference to protect the transistor from an undesired positive-going voltage transient; coupling a cathode of a second steering diode to the anode of the first steering diode and to the data line; and coupling an anode of the second steering diode to a second reference to protect the transistor from an undesired negative-going voltage transient.
- 24. The method as defined in claim 23, wherein the compound semiconductor is selected from a Group III-V compound semiconductor.
- 25. The method as defined in claim 23, wherein the compound semiconductor is selected from a Group IV compound semiconductor.
- 26. The method as defined in claim 23, further comprising:
fabricating a cathode for a breakdown diode from the N-type emitter layer; fabricating an anode for the breakdown diode from the P-type base layer; and coupling the cathode of the breakdown diode to the cathode of the first steering diode and coupling the anode of the breakdown diode to the anode of the second steering diode.
- 27. The method as defined in claim 23, wherein the first reference and the second reference are the same.
- 28. The method as defined in claim 23, wherein the first reference is a power supply line and the second reference is a ground.
- 29. A method of protecting a device on a monolithic gallium arsenide (GaAs) chip coupled to a signal line from undesired voltage transients, the method comprising:
clamping the signal line to a first positive voltage when the monolithic gallium arsenide (GaAs) chip is in a powered-on state in response to an undesired voltage transient with a positive-going spike, where the first positive voltage is a first multiple of a forward voltage drop of a monolithically integrated gallium arsenide (GaAs) diode above a power supply voltage that is supplied to the monolithic chip; clamping the signal line to a second positive voltage when the monolithic chip is in a powered-off state, where the second positive voltage is a sum of the first multiple of the forward voltage drop of the monolithically integrated gallium arsenide (GaAs) diode and a reverse breakdown voltage of a breakdown diode that is integrated into the monolithic chip, where the second positive voltage is referenced to ground; and clamping the signal line to a negative voltage that is a second multiple of a forward voltage drop of a monolithically integrated gallium arsenide (GaAs) diode below a ground potential in response to an undesired voltage transient with a negative-going spike.
- 30. The method as defined in claim 29, where the first multiple and the second multiple are a same value.
- 31. The method as defined in claim 29, where the first multiple and the second multiple are both a value of 1.
- 32. The method as defined in claim 29, further comprising clamping pluralities of signal lines through pluralities of steering diodes on the monolithic chip, where the pluralities of steering diodes are coupled to a same breakdown diode.
RELATED APPLICATION
[0001] This application is a divisional application of U.S. application Ser. No. 10/096,995, entitled “COMPOUND SEMICONDUCTOR PROTECTION DEVICE FOR LOW VOLTAGE AND HIGH SPEED DATA LINES,” filed Mar. 12, 2002.
Divisions (1)
|
Number |
Date |
Country |
Parent |
10096995 |
Mar 2002 |
US |
Child |
10261362 |
Sep 2002 |
US |