The present invention relates to methods for producing memory cell arrays. In particular, the present invention relates to methods that are suitable to be used for planar EEPROMS for so-called “stand-alone” applications and for so-called “embedded” applications.
One of the most important development aims in the field of memory cells is the realization of increasingly smaller memory cells, i.e., the use of increasingly smaller chip areas per bit stored. Up to now, it has been considered advantageous to realize compact cells by means of buried, i.e., diffused bit lines. However, bit lines implemented as diffusion areas become increasingly high ohmic as their structural size decreases, since the diffusion depth must be scaled as well, so as to counteract the risk of a punch through between neighboring bit lines. The problem arising in this connection is that high-ohmic bit lines permit only comparatively small cell blocks so that the utilization degree decreases and the advantage of the smaller memory cells, for which a higher process expenditure must be tolerated, diminishes.
One example of known memory cells with buried bit lines and a virtual-ground-NOR architecture is described in the article: “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell”, Boaz Eitan et al, IEEE Electron Device Letters, Vol. 21, No. 11, November 2000, pp. 543-545, which is incorporated herein by reference. These concepts increase the resolution capabilities in semiconductor manufacturing. However, significant efforts and investments are needed to produce memories having the best possible resolution capabilities.
A further example of known memory cells is described in U.S. Pat. No. 6,686,242, which is incorporated herein by reference. A method for producing bit lines for a memory cell array comprises as a first step the step of providing a layer structure that comprises a substrate having transistor wells implanted in a surface thereof, a sequence of storage medium layers provided on the surface of the substrate, and a gate region layer provided on the sequence of storage medium layers. Bit line recesses, which extend down to the sequence of storage medium layers, are produced in the gate region layer. Subsequently, insulating spacer layers are produced on lateral surfaces of the bit line recesses, whereupon a source/drain implantation is executed in the area of the bit line recesses, after a complete or partial removal of the sequence of storage medium layers.
Following this, the substrate is exposed completely in the area of the bit line recesses, if this has not yet been done prior to the implantation. Subsequently, metallizations for producing metallic bit lines are produced on the exposed substrate, the metallizations being insulated from the gate region layer by the insulating spacer layers.
In various embodiments, the present invention provides methods and devices that permit the realization of very compact memory cells.
According to a first aspect of the present invention, a method is provided for fabricating nonvolatile memory cells. A structured charge trapping layer is deposited on the surface of a semiconductor wafer. A plurality of gate lines are deposited on top of the structured charge trapping layer. An insulating spacer is deposited on the side walls of the plurality of gate lines. A plurality of buried bit lines are formed. Each of the buried bit lines is embedded in the substrate as a diffusion region. An insulating layer is deposited within the region between the plurality of gate lines and the structured charge trapping layer. An etch stop layer is deposited on top of the insulating layer. A dielectric layer is deposited on the top of the etch stop layer. The dielectric layer is etched to form contact holes ranging from the surface of the dielectric layer to the surface of the etch stop layer. The etch stop layer is etched to further enlarge the contact holes ranging from the surface of the dielectric layer to the surface of the insulating layer. The insulating layer is etched to further enlarge the contact holes ranging from the surface of the dielectric layer to the surface of the buried bit line. A contact plug is formed by filling the contact holes with a conductive plug material.
Yet another solution to the object is provided by a method for fabricating nonvolatile memory cells. A charge trapping layer is deposited on the surface of the semiconductor wafer. A conductive layer is deposited on top of the structured charge trapping layer. An insulating spacer is deposited on the side walls of the plurality of gate lines. A mask layer is deposited on top of the conductive layer. The mask layer is patterned so as to form a plurality of structural elements being arranged substantially parallel to each other. The conductive layer and the charge trapping layer are patterned using the plurality of structural elements as a hard mask so as to form gate lines being arranged between adjacent diffusion regions. A spacer oxide layer is deposited on the side walls of the plurality of gate lines, the structured charge trapping layer and the structural elements of the mask layer. Ions are implanted using the spacer oxide layer as a mask to form a plurality of buried bit lines within the substrate as diffusion regions. An insulating layer is deposited within the region between the plurality of gate lines and the structured charge trapping layer. The structural elements of the mask layer are removed. An etch stop layer is deposited on top of the insulating layer. A dielectric layer is deposited on the top of the etch stop layer. The dielectric layer is etched to form contact holes ranging from the surface of the dielectric layer to the surface of the etch stop layer. The etch stop layer is etched to further enlarge the contact holes ranging from the surface of the dielectric layer to the surface of the insulating layer. The insulating layer is etched to further enlarge the contact holes ranging from the surface of the dielectric layer to the surface of the buried bit line. A contact plug is formed by filling the contact holes with a conductive plug material.
Yet another solution to the object is provided by a method for fabricating nonvolatile memory cells. A structured charge trapping layer is deposited on the surface of the semiconductor wafer. A plurality of gate lines are deposited on top of the structured charge trapping layer. An insulating spacer is deposited on the side walls of the plurality of gate lines. A plurality of buried bit lines are formed. Each of the buried bit lines is embedded in the substrate as a diffusion region. A bit line insulating layer is deposited above the bit lines. An etch stop layer is deposited on top of the insulating layer. A dielectric layer is deposited on the top of the etch stop layer. The dielectric layer is etched to from contact holes ranging from the surface of the dielectric layer to the surface of the etch stop layer. The etch stop layer and the insulating layer are etched to further enlarge the contact holes ranging from the surface of the dielectric layer to the surface of the buried bit line. A contact plug is formed by filling the contact holes with a conductive plug material.
Yet another solution to the object is provided by a method for fabricating nonvolatile memory cells. A structured charge trapping layer is deposited on the surface of the semiconductor wafer. A plurality of gate lines is deposited on top of the structured charge trapping layer. An insulating spacer is deposited on the side walls of the plurality of gate lines. A plurality of buried bit lines are formed. Each of the buried bit lines is embedded in the substrate as a diffusion region. A bit line insulating layer is deposited above the bit lines covering the bit lines in a region between the gate lines. An etch stop layer is deposited on top of the insulating layer. The etch stop layer is etched to form a partially removed etch stop layer so as to uncover the top surface of bit line insulating layer. A dielectric layer is deposited on the top of the etch stop layer. The dielectric layer is etched to form contact holes ranging from the surface of the dielectric layer to the surface of the insulating layer. The insulating layer is etched to further enlarge the contact holes ranging from the surface of the dielectric layer to the surface of the buried bit line. A contact plug is formed by filling the contact holes with a conductive plug material.
Yet another solution to the object is provided by a method for fabricating nonvolatile memory cells. A structured charge trapping layer is deposited on the surface of the semiconductor wafer. A plurality of gate lines is deposited on top of the structured charge trapping layer. An insulating spacer is deposited on the side walls of the plurality of gate lines. A plurality of buried bit lines are formed. Each of the buried bit lines is embedded in the substrate as a diffusion region. A bit line insulating layer is deposited above the bit lines covering the bit lines in a region between the gate lines. An etch stop layer is deposited on top of the insulating layer. The etch stop layer is etched to form a partially removed etch stop layer having a smaller thickness on the top surface of the bit line insulating layer. A dielectric layer is deposited on the top of the etch stop layer. The dielectric layer is etched to form contact holes ranging from the surface of the dielectric layer to the surface of the etch stop layer. The partially removed etch stop layer and the insulating layer is etched to further enlarge the contact holes ranging from the surface of the dielectric layer to the surface of the buried bit line. A contact plug is formed by filling the contact holes with a conductive plug material.
The above features of the present invention will be more clearly understood from consideration of the following descriptions in connection with accompanying drawings in which:
A presently preferred embodiment of the method for fabricating non-volatile memory cells having self-aligned bit line contacts and a non-volatile memory cell having self-aligned bit line contacts according to embodiments of the invention is discussed in detail below. It is appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to apply the method and to apply the memory cell of the invention, and do not limit the scope of the invention.
In the following, embodiments of the method for fabricating non-volatile memory cells having self-aligned bit line contacts and a non-volatile memory cell having self-aligned bit line contacts are described with respect to NROM memories of the virtual ground architecture having a plurality of non-volatile memory cells.
With respect to
Before preferred embodiments for methods of producing a memory cell array will be explained in detail, the general arrangement of the resulting bit lines and word lines of a virtual-ground-NOR architecture will be described making reference to
In such a virtual-ground architecture respective memory cells 6 are arranged below the word lines 2 between the bit lines 8, as indicated in
As shown in
Referring now to
The semiconductor wafer 12 has a semiconductive substrate 14. Processing further includes conformably depositing a charge-trapping layer 16 on the semiconductive substrate 14. The step of conformably depositing the charge-trapping layer 16 includes depositing an oxide/nitride/oxide-layer stack. As an example, the oxide/nitride/oxide-layer stack has a thickness 18 of less than about 50 nm, preferably in a range between about 5 nm and about 30 nm.
Next, a conductive layer 20 is deposited on top of the charge-trapping layer 16. As an example, the conductive layer 20 is provided as a polysilicon layer. Subsequently, a mask layer 22 is deposited on top of the conductive layer 20. As an example, the step of depositing a mask layer 22 on the surface of the conductive layer 20 can be employed by depositing a nitride layer. In general, the mask layer 22 should have a high etching resistance against the materials of the semiconductive substrate 14, the charge-trapping layer 16 and the conductive layer 18.
In a next step, the mask layer 22 is lithographically patterned, so as to form structural elements 24 of the mask layer 22 on the surface of conductive layer 20. The patterning of the mask layer 22 includes depositing a resist layer on the surface of the mask layer 22 and lithographically patterning the resist layer to form a patterned resist layer. After removing the mask layer 22 outside the patterned resist layer by etching, the patterned resist layer can be removed.
Now, the structural elements 24 of the mask layer 22 are used as an etch mask in order to etch the conductive layer 20 and the charge-trapping layer 16. This etching step is performed selective to the patterned mask layer 22 by employing an anisotropic etching step, e.g., by reactive ion etching. Other suitable etching processes might be used as well.
As a result, gate lines are formed from the conductive layer 20 that cover the patterned charge-trapping layer 16 thus creating a region between the gate lines whereas the surface 26 of the semiconductive substrate 14 is substantially uncovered. It is, however, conceivable that residues, e.g., a thin bottom oxide layer remain on the surface 26 of the semiconductive substrate 14. Within this region, diffusion regions are formed from the surface 26 of the semiconductive substrate 14 into a certain depth, as shown in
A spacer 36 is deposited on the side walls of the gate lines 28, preferably as a silicon oxide layer.
In a next step, the oxide spacer layer 36 is used as an implantation mask. Using ions being selected with a proper energy the buried bit lines 8 are formed as an implanted region in the substrate 14 between the side walls of the oxide spacer layer 36. This step is performed to achieve optimized junction implants for the source/drain regions and thus the bit lines 8. Usually, this implantation is followed by a thermal anneal process sequence.
In a next step, an insulating layer 38 is deposited between the gate lines 28, as shown in
First, the insulating layer 38 is conformably deposited as a silicon dioxide layer. The insulating layer 38 covers the recesses between the gate lines 28 and the structural elements 24 of the mask layer 22. Next, the insulating layer 38 is removed from the top side of the hardmask 22 by employing a chemical mechanical polishing step.
In summary, etching and implanting of the semiconductor wafer 12 creates an insulating layer 38 that is arranged above the bit lines 8, as shown in
Processing continues by removing the structural elements 24 of the mask layer 22, e.g., by employing a wet-etch step. At that stage of the processing several other process steps might be envisaged, including deposition of a word line layer or layer stack and patterning the word line 2. Forming word lines 2 is known to a person skilled in the art and is, therefore, not described in further detail.
In a next step, a etch stop layer 50 is conformably deposited on the surface of the semiconductor wafer 12, as shown in
In a next step, a dielectric layer 60 is conformably deposited on the etch stop layer 50. The dielectric layer 60 is deposited as a BPSG layer, i.e., a boron phosphate silica glass layer. The dielectric layer 60 serves as a dielectric for an interconnecting metal layer, which is later deposited on the surface of the dielectric layer 60 (not shown in
In a next step, dielectric layer 60 is patterned so as to form contact holes 40 at those positions that are to be connected by the bit line contact 10. The patterning of the dielectric layer 60 includes depositing a resist layer on the surface of the dielectric layer 60, lithographically patterning the resist layer to form a patterned resist layer, and etching the dielectric layer 60 to form contact holes 40. Instead of using a lithographically patterned the resist layer, a hard mask layer can be used as well.
The resulting structure is shown in
In
Next, the contact holes 40 are further enlarged in a direction perpendicular to the surface of semiconductor wafer 12, as shown in
In a first possible process sequence, the etch stop layer 50 is etched for a given time period so as to completely etch the etch stop layer 50 in the region of the contact holes 40. In a second possible process sequence, the etch stop layer 50 is etched and the resulting etched materials are monitored in order to determine an end point when reaching insulating layer 38.
In a next step, the contact holes 40 are further enlarged in a direction perpendicular to the surface of semiconductor wafer 12, as shown in
Processing further continues by depositing a contact plug material in the contact holes 40 above the bit lines 8. The contact holes 40 are then filled with conductive material so as to form a contact plug 10 at certain positions within the memory cell array, as shown in
According to the process sequence described above, contacting the buried bit line 8 is performed using a self-aligned scheme. The self-aligned processing greatly reduces the risk of accidentally contacting elements surrounding the bit lines 8 by using the self alignment of the insulating layer 38 and the different etching selectivity of insulating layer 38, etch stop layer 50 and dielectric layer 60.
With respect to
Referring now to
In general, the insulating layer 38 has a high etching selectivity to the later applied dielectric layer and the material of insulating layer 38 is chosen accordingly.
Processing continues by removing the structural elements 24 of the mask layer 22, e.g., by employing a wet-etch step. At that stage, forming word lines 2 can be performed.
In a next step, the etch stop layer 50 is conformably deposited on the surface of the semiconductor wafer 12, as shown in
In a next step, a dielectric layer 60 is conformably deposited on the etch stop layer 50. Again, the dielectric layer 60 is deposited as a BPSG layer. In a next step, dielectric layer 60 is patterned, so as to form contact holes 40 at those positions that are to be connected by the bit line contact 10. The patterning of the dielectric layer 60 is either performed lithographically or using a hardmask layer utilizing the different etching selectivity between different layer materials.
The resulting structure is shown in
Next, the contact holes 40 are further enlarged in a direction perpendicular to the surface of semiconductor wafer 12, as shown in
Processing further continues by depositing a contact plug material in the contact holes 40 above the bit lines 8. The contact holes 40 are then filled with conductive material so as to form a contact plug 10 at certain positions within the memory cell array, as shown in
With respect to
After removing the structural elements 24 of the mask layer 22 and forming of word lines 2 the etch stop layer 50 is conformably deposited on the surface of the semiconductor wafer 12, as shown in
In a next step, the etch stop layer 50 is etched so as to release the surface of the insulating layer 38. At that point a partially removed etch stop layer 55 is formed, as shown in
In a next step, a dielectric layer 60 is conformably deposited on the partially removed etch stop layer 55 and on the released surface of the insulating layer 38. Again, the dielectric layer 60 can be deposited as a BPSG layer.
In a next step, dielectric layer 60 is patterned, so as to form contact holes 40 at those positions that are to be connected by the bit line contact 10. The patterning of the dielectric layer 60 is either performed lithographically or using a hardmask layer. The resulting structure is shown in
Next, the contact holes 40 are further enlarged in a direction perpendicular to the surface of semiconductor wafer 12, as shown in
Subsequently, further metal interconnecting layers can be provided as described previously.
Referring now to
In a next step, the etch stop layer 50 is thinned by etching. Opposed to the embodiment of
In a next step, a dielectric layer 60 is conformably deposited on the partially removed etch stop layer 55. Again, the dielectric layer 60 can be deposited as a BPSG layer.
In a next step, dielectric layer 60 is patterned, so as to form contact holes 40 at those positions that are to be connected by the bit line contact 10. The patterning of the dielectric layer 60 is either performed lithographically or using a hardmask layer. The resulting structure is shown in
Next, the contact holes 40 are further enlarged in a direction perpendicular to the surface of semiconductor wafer 12, as shown in
Subsequently, further metal interconnecting layers can be provided as described previously.
The further embodiments of the invention as shown with respect to
Having described embodiments for a method for fabricating non-volatile memory cells and non-volatile memory cells, it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is, therefore, to be understood that changes may be made in the particular embodiments of the invention disclosed, which are within the scope and spirit of the invention as defined by the appended claims.
Having thus described the invention with the details and the particularity required by the patent laws, what is claimed and desired to be protected by Letters Patent is set forth in the appended claims.