The present invention relates to semiconductor processes, and in particular to methods for fabricating a trench isolation structure having better height uniformity.
An isolation structure of a semiconductor device is generally provided to electrically isolate semiconductor elements such as transistors, resistors, and capacitors in an active region from other semiconductor elements in a neighboring active region on a same semiconductor substrate.
At present, the isolation structure that is often used includes a trench isolation structure, wherein neighboring active regions are electrically isolated from one another by a trench formed vertically in the semiconductor substrate filled with an isolation dielectric. The isolation dielectric is typically made of silicon oxide (SiO2). The trench is formed in the substrate according to the desired pattern of an isolation region, and then the isolation dielectric is formed to fill the trench to form a trench isolation structure. However, the height (or thickness) uniformity of the trench isolation structure is usually not good.
In some embodiments of the disclosure, a method for fabricating a trench isolation structure is provided. The method includes providing a substrate, forming a patterned mask layer on the substrate, performing a first etching step to the substrate by using the patterned mask layer to form a trench in the substrate, and forming a dielectric material in the trench and on the patterned mask layer, wherein the dielectric material on the patterned mask layer has a first height. The method also includes performing an etch back step to decrease the dielectric material on the patterned mask layer from the first height to a second height, and performing a planarization process to remove the dielectric material on the patterned mask layer, wherein a polishing pad is used during the planarization process, a first pressure is applied on a central portion of the polishing pad, a second pressure is applied on a peripheral portion of the polishing pad, and the second pressure is greater the first pressure.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is about methods for fabricating a trench isolation structure according to embodiments of the disclosure. However, it should be appreciated that the embodiments of the disclosure provide lots of suitable concepts of the invention and can be performed in a wide variety of specific backgrounds. The specific embodiments of the disclosure are used to explain the fabrication by specific methods and use of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. Moreover, the same or similar elements in the drawings and the description are labeled with the same reference numbers.
Refer to
Refer to
As shown in
Refer to
In
In
Refer to
As shown in
Refer to
Since the etching step 140 is applied with a dry-etching process which has a higher etch selectivity ratio to the dielectric material compared to a traditional dry-etching process (the traditional dry-etching process has an etch selectivity ratio of the patterned mask layer to the dielectric material that is 1:7-1:8), i.e. the dry-etching process of the disclosure has an etching rate to the dielectric material 107b1 that is much higher than the etching rate to the patterned mask layer 114. Therefore, the etching step 140 does not damage to the patterned mask layer 114, and surface non-uniformity of the silicon nitride layer 113 of the patterned mask layer 114 is thereby avoided.
Refer to
Refer to
Since the second pressure P2 applied on the peripheral portion 200b of the polishing pad 200 is greater than the first pressure P1 applied on the central portion 200a of the polishing pad 200, an edge impress control to the peripheral portion of the polishing pad 200 is enhanced, and the problem of a poor polishing rate to the peripheral portion of the polishing pad in a traditional chemical mechanical polishing process is thereby overcome. Therefore, the top surface of the patterned mask layer 114 is level with the top surface of the dielectric layer 107a1 in
Before the planarization process 150 being performed, the etch back step 130 and the etching step 140 have been performed to remove the dielectric material 107b1 on the patterned mask layer 114 and a portion of the dielectric material 107a1 higher than the top surface of the patterned mask layer 114. Therefore, the etch back step 130 and the etching step 140 can reduce the process load of the planarization process 150 of removing the aforementioned dielectric material 107a1 and 107b1.
After the planarization process 150 has been performed, a multi-point measurement of the height (or thickness) is performed on the dielectric material 107a1 in the trench 101a and the silicon nitride layer 113 included in the patterned mask layer 114. The measurement of the height of the dielectric material 107a1 is referred to as the vertical height h3 of the dielectric material 107a1 from the surface of the dielectric material 107a1 to the bottom of the trench 101a. The vertical height h3 is also called the trench step height. In the embodiment, through the combination of the etch back step 130, the etching step 140, and the planarization process 150 including the edge impress control to the peripheral portion of the polishing pad, experimental data shows that the amount of measurement samples that exceed the average height of the dielectric material 107a1 by three standard deviations is about 5% of the entire amount of measurement samples. The amount of measurement samples which exceed the average height of the silicon nitride layer 113 by three standard deviations is about 20.1% of the entire amount of measurement samples. In a comparative example, methods for fabricating an isolation structure do not include the etch back step 130 in the embodiment, and the methods use traditional planarization process (i.e. pressures applied to the center of the polishing pad and the edge of the polishing pad are identical). In the comparative example, experimental data shows that the amount of measurement samples which exceed the average height of the dielectric material 107a1 by three standard deviations is about 10.1% of the entire amount of measurement samples, and the amount of measurement samples which exceed the average height of the silicon nitride layer 113 of the patterned mask layer 114 by three standard deviations is about 38.7% of the entire amount of measurement samples.
It can be learned from the embodiment and the comparative example that, through the combination of the etch back step 130, the etching step 140, and the planarization process 150 including the edge impress control to the peripheral portion of the polishing pad, the ratio of the amount of measurement samples which exceed the average height of the dielectric material 107a1 in the trench 101a by three standard deviations to the entire amount of measurement samples can be reduced, and the ratio of the amount of measurement samples which exceed the average height of the silicon nitride layer 113 of the patterned mask layer 114 by three standard deviations to the entire amount of measurement samples can be reduced. Namely, in the embodiment, the height of the dielectric material 107a1 in the trench 101a in any point of measurement range is closer to its average height, and the height of the silicon nitride layer 113 in any point of measurement range is closer to its average height. In other words, the trench step height of the dielectric material 107a1 in the trench 101a and the thickness of the silicon nitride layer 113 included in the patterned mask layer 114 have better uniformity.
Refer to
In traditional technology, after a trench isolation structure is formed, a step of conformally forming a polysilicon layer over an active region and the trench isolation structure and a step of removing the polysilicon layer over the trench isolation structure are included. Since the top surface of the traditional trench isolation structure is more uneven, the polysilicon layer would be left on the top surface of the trench isolation structure after the etching process, and the isolation function of the trench isolation structure is thereby damaged.
Since the dielectric material 107a1 of the trench isolation structure 100 fabricated according to some embodiments of the disclosure has better height (or thickness) uniformity, the top surface of the trench isolation structure 100 is more even, and subsequently formed elements (not shown) in the active region on both sides of the trench isolation structure 100 are thereby prevented from being left on the top surface of the trench isolation structure 100 and damaging the isolation function of the trench isolation structure 100. Therefore, the reliability and the yield of the devices are thereby enhanced.
According to some embodiments of the disclosure, the rounding corner is formed from a top corner of the trench by the top corner rounding process, and a leakage current produced during the operation of the devices is thereby avoided. Therefore, the top corner rounding process of the trench can enhance the reliability of the devices. Moreover, since the rounding corner of the trench protrudes outward, an entire average width of the trench is smaller than the top width of the trench. Therefore, an aspect ratio of the trench can be enhanced.
In addition, through the etch back step, the height of the protruding portion of the dielectric material on the patterned mask layer is effectively decreased, which is an advantage to the subsequent step of removing the dielectric material.
Moreover, through the second pressure applied on the peripheral portion of the polishing pad is greater than the first pressure applied on the central portion of the polishing pad, the problem of a poor polishing rate to the peripheral portion of the polishing pad in a traditional chemical mechanical polishing process is solved. Therefore, the top surface of the patterned mask layer is level with the top surface of the dielectric layer and has better surface height (or thickness) uniformity.
Furthermore, through the etch back step and the subsequent etching step, the process load of the planarization process can be reduced, and the trench step height of the dielectric material in the trench and the silicon nitride layer included in the patterned mask layer have better height (or thickness) uniformity.
The method of fabricating the trench isolation structure according to the embodiments of the disclosure can be applied to metal oxide semiconductor field effect transistors (MOSFET) and a driving chip of liquid-crystal displays (LCD).
While the disclosure has been described by way of example and in terms of the embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Number | Name | Date | Kind |
---|---|---|---|
5665202 | Subramanian | Sep 1997 | A |
5721172 | Jang | Feb 1998 | A |
5783488 | Bothra | Jul 1998 | A |
5923993 | Sahota | Jul 1999 | A |
6022807 | Lindsey, Jr. | Feb 2000 | A |
6033970 | Park | Mar 2000 | A |
6048775 | Yao | Apr 2000 | A |
6169012 | Chen | Jan 2001 | B1 |
6184141 | Avanzino | Feb 2001 | B1 |
6242322 | Chen | Jun 2001 | B1 |
6261957 | Jang | Jul 2001 | B1 |
6342429 | Puchner | Jan 2002 | B1 |
6489242 | Nagahara | Dec 2002 | B1 |
6541382 | Cheng | Apr 2003 | B1 |
6558232 | Kajiwara | May 2003 | B1 |
6897121 | Lee | May 2005 | B2 |
7199018 | Hung | Apr 2007 | B2 |
7759214 | Yoon | Jul 2010 | B2 |
20030216104 | Korovin | Nov 2003 | A1 |
20040147205 | Golzarian | Jul 2004 | A1 |
20050000940 | Iwamoto | Jan 2005 | A1 |
20050003668 | Hung | Jan 2005 | A1 |
20050142800 | Choi | Jun 2005 | A1 |
20050159007 | Chen | Jul 2005 | A1 |
20050255668 | Tseng | Nov 2005 | A1 |
20060043071 | Lee | Mar 2006 | A1 |
20070224918 | Terada | Sep 2007 | A1 |
20120292748 | Sadaka | Nov 2012 | A1 |
20140015107 | Chen | Jan 2014 | A1 |
20150279686 | Kuo | Oct 2015 | A1 |
20150311093 | Li | Oct 2015 | A1 |
Number | Date | Country |
---|---|---|
10-1998-082731 | Dec 1998 | KR |
10-2002-002568 | Apr 2002 | KR |
10-2004-0036757 | May 2004 | KR |
200409235 | Jun 2004 | TW |
200707630 | Feb 2007 | TW |
201225212 | Jun 2012 | TW |
Entry |
---|
Korean Office Action and English translation, dated Sep. 20, 2017, for Korean Application No. 10-2016-0105651. |
Number | Date | Country | |
---|---|---|---|
20170372944 A1 | Dec 2017 | US |