Patent Application
20060134863
1. Field of the Invention
The present invention relates to wordlines, and in particular to methods of reducing wordline sheet resistance.
2. Description of the Related Art
In a typical flash or EEPROM memory array, the memory cells are arranged in a rectangular array of rows and columns to form intersections at which there are disposed memory cell transistors. The drain of each transistor is connected to a corresponding bit line, the source of each transistor is connected to an array source voltage by an array source line, and the gate of each transistor is connected to a wordline.
Tungsten has been used for wordline applications in semiconductor memory. However, the associated sheet resistance is conventionally not as low as may be desired for certain applications.
The present invention relates to methods and systems for reducing sheet resistance via the modification of poly and tungsten-silicide (WSix, where x can be, for example 1 or 2) films with additional implantation. By way of example, the wordlines can be associated with a non-volatile semiconductor memory circuit, such as a flash or EEPROM memory device, or a volatile semiconductor memory circuit.
In one embodiment, a first poly-Si portion is deposited on a semiconductor substrate using a first precursor gas flow rate. A second poly-Si portion is deposited using a second precursor gas flow rate, where the second precursor flow rate higher than the first precursor gas flow rate. A tungsten silicide layer is deposited using silane gas. Wordlines are formed in trenches from poly-Si and WSix. A gate electrode is implanted.
One example embodiment is a method of forming memory wordlines, the method comprising: forming a first gate dielectric; forming a charge storage layer on the first gate dielectric; forming a second dielectric layer on the charge storage layer; depositing a first poly-Si portion using a gas with a first gas flow rate; depositing a second poly-Si portion using the gas with a second gas flow rate, the second gas flow rate higher than the first gas flow rate; depositing a tungsten silicide layer with silane gas, wherein wordlines are formed in isolation trenches from a stacked film of poly-Si and tungsten silicide; and implanting a gate electrode.
Another example embodiment is a method of depositing tungsten to form wordlines, the method comprising: depositing on the semiconductor substrate a first poly-Si portion with a first precursor gas flow rate; depositing a second poly-Si portion with a second precursor gas flow rate, the second precursor flow rate higher than the first precursor gas flow rate; performing gate implantation using an implantation energy within the range of about 30 to 100 KeV; and depositing a WSix layer, wherein wordlines are formed from poly-Si and WSix.
Yet another example embodiment is a method of forming memory wordlines, the method comprising: depositing a first poly-Si portion using a gas with a first gas flow rate; depositing a second poly-Si portion using the gas with a second gas flow rate, the second gas flow rate higher than the first gas flow rate; depositing WSix and forming wordlines; and implanting a gate electrode.
Exemplary embodiments of the present invention are illustrated in the accompanying drawings, which are for illustrative purposes only. The drawings comprise the following figures, in which like numerals indicate like parts.
The present invention relates to memory device wordlines, and in particular to methods of reducing sheet resistance via the modification of poly and tungsten-silicide (WSix) films with additional implantation. By way of example, the wordlines can be associated with a non-volatile semiconductor memory circuit, such as a flash or EEPROM memory device, or a volatile semiconductor memory circuit.
Tungsten-silicide can have one or more advantageous characteristics for use with wordlines, such as having low resistance and low stress.
In particular, in one embodiment, selected processing parameters, including the gas flow of deposition precursors, such as PH3 or WF6, and/or an additional implantation processes, are used to reduce the wordline sheet resistance. In particular, in one example, the modulation of poly-Si (utilizing an example two-step process described below) and post-WSi deposition implantation reduces wordline sheet resistance about 24%-25%, although greater or lower reductions can optionally be achieved.
While the examples discussed herein relate to memory wordlines for illustrative purposes, embodiments of the present invention is applicable to the formation of other types of interconnects and/or other types of semiconductor devices.
A substrate, which can be for example, a silicon substrate, has well engineering performed to form a well region. The well region can be formed using, for example, a well ion implantation process. In addition, a first gate dielectric is formed thereon. Overlaying the first gate dielectric is a charge storage layer, which can be, for example, a floating-gate-poly layer (poly-Si, high-dose P doped) or other charge trapping materials. The next layer in this example includes a second dielectric layer followed by a control-gate poly layer.
A WSix layer is deposited using a WSi deposition process. A gate electrode patterning process is then performed, followed by spacer and source/drain engineering. The WSix layer overlays the control gate layer and forms a low-resistance interface between wordlines deposited in isolation trenches and the control gates. The wordlines can include a stacked film of (poly-Si+WSi).
Example fabrication parameters for the gate electrode, including poly-Si and WSi fabrication processes, are as follows, although other process parameters, including other facilities, process conditions, and/or process steps can be used:
1. Poly-Si Deposition:
(a) Facility: CVD (chemical vapor deposition) including a single-wafer (or multi-wafer) process chamber and a furnace.
(b) Process conditions: 600° C. to 800° C., 0.3 torr to 400 torr, wherein the gas flow rates of SiH4 and PH3 (for P-doped poly-Si) not generally limited. The process time can be 20 sec to 2 hours, although other ranges can be used.
(c) An example “two-step” poly-Si deposition process with increased PH3 gas flow rate is optionally performed, although additional steps can be performed as well.
1st step: deposit the first part of doped poly-Si with a relatively low first PH3 gas flow rate, such as, by way of example, less than 200 sccm, or, in one embodiment, about 80 sccm (standard cubic centimeters per minute).
2nd step: deposit the second part of doped poly-Si overlying the first part of poly-Si using a second gas flow rate. The second gas flow rate and P concentration is relatively higher than for the deposit of the first portion of the doped poly-Si. For example, the gas flow can be about 20 sccm higher than the first PH3 gas flow, such as a gas flow rate of 100 sccm for example, or in one embodiment, less than or equal to 400 sccm, in the second part will be higher than that in first part of poly-Si.
2. WSix Deposition:
(a) Facility: single-wafer (or multi-wafer) CVD chamber.
(b) Process condition: In one example process, the reactants include at least one silane-based gas and one tungsten-based gas.
3. Implantation of the Gate Electrode:
(a) Facility: a variety of implanter-types can be used, including single-wafer or batch type implanters.
(b) Process Conditions:
Dosage: >1.0E14 (cm−2), for example a dosage of 5.5E15 can be used.
Energy: from 5 to 200 KeVo, or more preferably, 30 to 100 KeV.
Specie: One or more of P, As, B, BF2, In, Ge, Si, etc. For example, one embodiment utilizes P and As.
Optionally, before implantation, an additional screen layer on WSix can also be included, such as about 280 Angstroms using a LPTEOS (Low Pressure Tetraethoxysilane) deposition process.
At state 200, the substrate is prepared. By way of example, the preparation may optionally include one or more of a silicon wafer marking process, using a laser or other marking technology, well formation, and/or a thermal oxidation process to form an oxide film. At state 201 a first gate dielectric can be formed
Next, at state 202, a charge layer is formed. At state 203 transistor source and drain formation takes place. At state 204, a second dielectric is formed. At state 205, a control gate poly layer is formed. At state 206 a WSi layer is formed, and a WSi annealing process is performed. The annealing process can utilize a variety of different annealing processes, optionally including one or more of conventional annealing using a conventional furnace, annealing using RTP (rapid thermal processing) and an RTP furnace, and or other annealing processes and furnaces. For example, the RTP annealing process can be performed at about 800° C. to 1200° C., for 5 seconds to 120 minutes. By way of further example, the annealing can be performed at a first temperature for a first period of time, then at a second temperature higher than the first temperature for a shorter period of time. Optionally, a sacrificial cap or screen is formed using an LPTEOS (low pressure tetra-ethoxysilane) deposition process [not shown].
By way of example, the deposition process can provide a poly-Si layer within a range of about (500 Å to 2000 Å), and in one embodiment, of about 600 Å. The deposition process can provide a WSix layer within a range of about (500 Å to 2000 Å), and in one embodiment, of about 900 Å. Wordlines are formed in isolation trenches. The wordlines can be formed from a stacked film of WSix and poly-Si.
Thus, embodiments of the poly and WSi films and implantation processes disclosed herein can advantageously reduce wordline sheet resistance.
While the foregoing detailed description discloses several embodiments of the present invention, it should be understood that this disclosure is illustrative only and is not limiting of the present invention. It should be appreciated that the specific configurations and operations disclosed can differ from those described above, and that the methods described herein can be used in contexts other than flash memory.
