Claims
- 1. A method of erasing a nonvolatile memory cell in a chip, said cell comprising a semiconductor substrate including a source and a drain region and a channel therebetween, a floating gate extending over a portion of said channel, further referred to as the floating-gate channel, a control gate extending over another portion of the channel, further referred to as the control-gate channel, and a program gate capacitively coupled through a dielectric layer to said floating gate, said method comprising the steps of:
- applying a first negative voltage to said program gate;
- applying a third negative voltage to said control gate thereby establishing an electric field between said control gate and said substrate;
- said first and said third negative voltage coupling a second negative voltage to said floating gate;
- applying a fourth voltage equal or higher than the supply voltage of said chip to said drain region; and
- applying a fifth negative voltage to the substrate, said negative voltage being large enough to reduce the electric field between the control gate and the substrate and to couple a sixth negative voltage to the floating gate.
- 2. The method as recited in claim 1, wherein the first voltage is an on-chip generated voltage.
- 3. The method as recited in claim 1, wherein the fourth voltage is an on-chip generated voltage which is higher than the supply voltage of said chip.
- 4. The method as recited in claim 1, wherein the third voltage and fifth voltage are generated on-chip.
Priority Claims (1)
Number |
Date |
Country |
Kind |
98870108 |
May 1998 |
EPX |
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REFERENCE TO RELATED APPLICATIONS
This is a divisional application of U.S. patent application Ser. No. 09/149,723, filed Sep. 8, 1998 now U.S. Pat. No. 6,058,043.
This application claims priority benefits to U.S. provisional application Ser. No. 60/058,279, filed on Sep. 9, 1997, and to European Patent application EP 98870108.2 filed May 14, 1998.
US Referenced Citations (10)
Foreign Referenced Citations (2)
Number |
Date |
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0 741 415 |
Nov 1996 |
EPX |
0 762 429 |
Mar 1997 |
EPX |
Non-Patent Literature Citations (1)
Entry |
European Patent Office Search Report, Application No. EP 98 87 0108. |
Divisions (1)
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Number |
Date |
Country |
Parent |
149723 |
Sep 1998 |
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