This disclosure relates generally to computer vision and, more particularly, to methods, systems, apparatus, and articles of manufacture for monocular depth estimation.
The technical fields of computer vision, machine vision, image processing, pattern recognition, and the like, often involve the analysis of one or more images of a scene to extract features indicative of the objects within the scene and/or their spatial relationship to one another. The implementation of such technical disciplines may involve the generation of a depth map associated with the imaged scene. A depth map includes information indicative of the depth and/or distance of different surfaces of objects within the scene relative to a particular viewpoint of the image(s) being analyzed (e.g., relative to the viewpoint of the camera(s) that captured the image(s)). Some depth maps define a value representative of a depth for each pixel in an image of the scene being analyzed. The depth values for individual pixels defined in a depth map are estimations based on an analysis of the underlying image(s) of the scene.
In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. The figures are not necessarily to scale.
In some computer vision applications, depth information associated with an imaged scene may be analyzed in addition to the texture (e.g., color, brightness, etc.) of an image of the scene. In some examples, such depth information is represented by a depth map or depth image. A depth map may be represented as a two-dimensional array of data with elements corresponding respectively to the two-dimensional array of pixels in an associated image. That is, the value of each element in a depth map corresponds to an individual pixel in the associated image. In some examples, the value of each element in the depth map indicates and/or corresponds to the depth or distance of the surface of the object in the scene represented by the corresponding pixel in the captured image relative to some reference point (e.g., the position of the sensor that captured the image).
In some examples, the values of a depth map can represent metric depth and/or relative depth for corresponding pixels in the captured image. As used herein, metric depth refers to absolute depth values (e.g., in physical units such as meters, inches, etc.) corresponding to the pixels in the image. In contrast, relative depth refers to a ranking and/or ordering of the depth values of the pixels relative to other pixels of the image, with a scale of the depth values being unknown. Stated differently, relative depth refers to scale-invariant ratios and/or relationships between the depth values of corresponding pixels.
In some cases, metric depth of an image is useful for some downstream applications in computer vision and robotics, such as mapping, planning, navigation, object recognition, reconstruction of three-dimensional (3-D) scenes, and/or image editing. However, training a metric depth estimation model across multiple datasets can reduce accuracy of predictions output by the metric depth estimation model, especially when the multiple datasets include images with large variations in depth scale (e.g., indoor images compared to outdoor images). As a result, metric depth estimation models may overfit to specific datasets and, thus, may not generalize well to other datasets. In contrast, by factoring out metric scale, relative depth estimation models can be trained across multiple diverse datasets corresponding to varying depth scales and/or domains (e.g., indoor, outdoor, etc.). As a result, the relative depth estimation models generalize across the different domains without a reduction in accuracy of the relative depth values output by the relative depth estimation models. However, because the relative depth values do not indicate metric scale, the relative depth values may have lower utility in computer vision applications (e.g., compared to metric depth values).
Examples disclosed herein improve metric depth estimation for an image by training an example encoder-decoder architecture (e.g., a. encoder-decoder backbone) for relative depth estimation and adding one or more example heads (e.g., metric heads, prediction heads) trained for metric depth estimation. As used herein, a backbone refers to a feature-extracting neural network (and/or a portion thereof) that processes input data into an example feature representation. As used here, a head (e.g., a head model) refers to a neural network (and/or a portion thereof) that predicts and/or detects one or more example parameters (e.g., depth values) based on the feature representation. In some examples disclosed herein, the encoder-decoder architecture includes an example encoder (e.g., an encoder network) to receive the image as input and extract example features (e.g., feature maps, multi-channel feature maps) from the input image to generate a lower-dimensional representation (e.g., compared to the original spatial dimensions) of the input image. The encoder-decoder architecture further includes an example decoder (e.g., a decoder network) to generate one or more example outputs based on the lower-dimensional, or compressed, representation. In some examples, the outputs include example feature maps (e.g., multi-channel feature maps) at corresponding decoder layers of the decoder, where the decoder layers correspond to respective different spatial resolutions of the input image. In some examples, the decoder performs up-sampling of the feature maps from previous decoder layers to generate the feature map for a current decoder layer, and the feature map at a final decoder layer (e.g., corresponding to the spatial resolution of the input image and/or half the spatial resolution of the input image) is used to generate an example relative depth map corresponding to the input image. Examples disclosed herein utilize a depth prediction transformer (DPT) encoder-decoder architecture trained based on a Multiple Depth Estimation Accuracy with Single Network (MiDaS) framework. In some examples, a different encoder-decoder architecture may be used in addition, or as an alternative, to a DPT encoder-decoder architecture trained based on the MiDaS framework.
In some examples, the feature maps from the different decoder layers are provided to one of the metric heads corresponding to a domain type (e.g., indoor or outdoor) of the input image. Example depth estimation circuitry disclosed herein estimates, based on the feature maps and the relative depth map output by the encoder-decoder architecture, example metric depth values for one or more pixels of the input image. For example, the depth estimation circuitry executes, based on a first feature map corresponding to a first decoder layer (e.g., at a bottleneck of the encoder-decoder architecture), one or more example neural networks to determine example bin center positions for the pixel(s). In some examples, the bin center positions correspond to respective depth values (e.g., a depth distribution) along an example depth interval. In some examples, the depth estimation circuitry determines one or more attractor points for one or more subsequent decoder layers, and the depth estimation circuitry iteratively adjusts the bin center positions across the subsequent decoder layers based on differences between the attractor points and the bin center positions.
In some examples, the depth estimation circuitry determines the metric depth values for the corresponding pixel(s) based on a linear combination of the bin center positions and corresponding example bin probability values. For example, the depth estimation circuitry determines the bin probability values based on a log binomial distribution, where example parameters (e.g., mode and/or temperature) of the log binomial distribution are determined based on the relative depth map and/or example bin embeddings corresponding to a final decoder layer. In some examples, the depth estimation circuitry outputs an example metric depth map indicating the metric depth values at respective pixels of the image.
Advantageously, by implementing one or more metric heads for metric depth estimation along with an encoder-decoder architecture pre-trained for relative depth estimation, examples disclosed herein achieve a metric depth estimation model that can accurately estimate metric depth values for an image while enabling generalization across multiple datasets and/or domain types. Further, by using attractor points to iteratively adjust bin center positions across subsequent decoder layers, examples disclosed herein gradually refine and/or improve accuracy of resulting metric depth predictions. Additionally, examples disclosed herein utilize a log-binomial distribution to predict the bin probability values across the bin centers, which can result in improved accuracy of the metric depth predictions compared to when other techniques (e.g., a softmax function) are used to predict the bin probability values. By improving the accuracy of estimated metric depth information, examples disclosed herein can improve efficiency of a computing device by improving performance of downstream applications (e.g., computer vision applications, robotics applications, etc.) that utilize the metric depth information. Further, by providing a metric depth estimation model that generalizes across multiple datasets and/or domains, examples disclosed herein reduce a need for re-training of the model and/or for training of multiple models for the different datasets and/or domains, thereby reducing utilization of memory and/or computational power of the computing device.
In the illustrated example of
In the example of
In this example, the encoder 112 accesses the image 102 and extracts example features therefrom to generate an example latent representation (e.g., a feature map) of the image 102. In some examples, the encoder 112 corresponds to one or more encoder layers of a neural network implemented by the encoder-decoder architecture 110, where the encoder 112 extracts and/or identifies the features at the one or more encoder layers. The features can represent, for example, an object to which one or more of the pixels 106 correspond, whether the pixels 106 correspond to a surface or an edge of the object, etc. In some examples, new features are extracted at subsequent one(s) of the encoder layers, and the features are stored in corresponding new channels generated for the latent representation of the image 102. As a result, the feature dimensionality of the latent representation (e.g., the number of channels used to represent per-pixel information and/or features) increases across the encoder layers. Further, at the subsequent one(s) of the encoder layers, the encoder 112 clusters and/or groups regions of the image 102 based on the extracted features, such that the spatial resolution of the latent representation is reduced across the encoder layers. In some examples, the encoder 112 outputs the latent representation at an example bottleneck 116 of the encoder-decoder architecture 110, where the bottleneck 116 corresponds to a final encoder layer of the encoder neural network. In this example, the latent representation at the bottleneck 116 has a reduced spatial resolution (e.g., 1/32, 1/64, 1/128, etc.) compared to the image 102, but a greater feature dimensionality (e.g., 1024 features for the latent representation at the bottleneck 116 compared to three features for the image 102).
In some examples, based on the latent representation at the bottleneck 116, the decoder 114 generates an example relative depth map 118 corresponding to the image 102. For example, the decoder 114 corresponds to one or more example decoder layers of the neural network implemented by the encoder-decoder architecture 110, where the decoder 114 performs up-sampling of the latent representation across the one or more decoder layers. In some examples, the decoder 114 performs the up-sampling using bi-linear interpolation and/or transposed convolutions to increase the spatial resolution of the latent representation between subsequent one(s) of the decoder layers. In some examples, the decoder 114 doubles the spatial resolution between the subsequent one(s) of the decoder layers, and five of the decoder layers (e.g., corresponding to 1/32, 1/16, ⅛, ¼, and ½ of the spatial resolution of the image 102) are used in this example. In some examples, the number of the decoder layers and/or the corresponding spatial resolutions can be different.
Further, as the decoder 114 up-samples the latent representation across the subsequent one(s) of the decoder layers, the decoder 114 reduces the feature dimensionality of the latent representation (e.g., the number of channels and/or features represented per pixel 106). For example, the number of features per pixel can be halved at subsequent one(s) of the decoder layers (e.g., such that the latent representation includes 1024 features per pixel at the bottleneck 116, 512 features per pixel at a first decoder layer, 256 features per pixel at a second decoder layer, etc.). In the example of
In the illustrated example of
In some examples, based on the first one of the feature maps 120 corresponding to the bottleneck 116, the depth estimation circuitry 200 of
In the illustrated example of
In some examples, example domain classification circuitry 208 of the depth estimation circuitry 200 of
For example,
In the illustrated example of
In some examples, a feature dimensionality (e.g., a number of features and/or channels) of the feature maps 120 can vary between layers (e.g., between the bottleneck 116 and/or the decoder layers 310), and/or can vary based on a type of architecture used for the encoder-decoder architecture 110 of
In the example of
In the illustrated example of
In the example of
In some examples, the bin selection circuitry 212 determines adjusted positions for the bin centers 302 at the first decoder layer 310A based on differences between the initial positions (e.g., first positions) for the bin centers 302 (e.g., from the bottleneck 116) and the attractors 320. For example, the bin selection circuitry 212 determines the adjusted position for an ith one of the bin centers 302 (e.g., where i=1, N, and N is the total number of the bin centers 302) based on example Equation 1 below.
c′
i
=c
i
+Δc
i (Equation 1)
In example Equation 1 above, c′i represents the adjusted position for the one of the bin centers 302 along the depth interval 314, ci represents the initial position for the ith one of the bin centers 302 along the depth interval 314, and Δci represents an example adjustment value for the one of the bin centers 302. In some examples, the bin selection circuitry 212 determines the adjustment value (e.g., Δci) based on an example inverse attractor equation shown in example Equation 2 below.
In example Equation 2 above, na represents a total number of the attractors 320 for a corresponding decoder layer 310, ak represents the position of a kth one of the attractors 320 along the depth interval 314, and a and γ represent example hyperparameters that determine strength of the attractors 320. Values for the hyperparameters can be present in the bin selection circuitry 212 and/or can be selected based on example user input(s) 220 to the depth estimation circuitry 200 of
In some examples, instead of using the inverse attractor equation shown in Equation 2 above, the bin selection circuitry 212 can determine the adjustment value Δci based on an example exponential attractor equation shown in example Equation 3 below.
Δci=Σk=1n
In some examples, the bin selection circuitry 212 can select one of the inverse attractor equation (shown in example Equation 2 above) or the exponential attractor equation (shown in example Equation 3 above) based on the user input(s) 220 to the depth estimation circuitry 200 of
In the illustrated example of
The example bin selection process flow 300 of
Returning to
In the example of
In some examples, the dimensionality of the bin array 124 (e.g., W×H×N) is different from the dimensionality of the output array 126 (e.g., W×H×(C+1)). Thus, to enable information represented in the bin array 124 to be combined with information represented in the output array 126, the depth estimation circuitry 200 of
In the example of
In example Equation 4 above, pk represents the probability value corresponding to the kth one of the bin centers 302 for a corresponding pixel 106, and N is the total number of the bin centers 302 determined for the corresponding pixel 106. In some examples, the probability value represent a probability that a depth value of the corresponding pixel 106 corresponds to the depth value associated with the/eh one of the bin centers 302. In some examples, the probability calculation circuitry 216 normalizes the probability values (e.g., pk) by determining a logarithm of the probability value(s) (e.g., log(p k)), utilizing Stirling's approximation for factorials, and applying a softmax function as shown in example Equation 5 below.
p′
k=softmax({log(pk)/t}k=1N) (Equation 5)
In example Equation 5 above, p′k represents the normalized probability values for the corresponding kth one of the bin centers 302. In some examples, the probability calculation circuitry 216 generates the probability array 128 based on the probability values pk (or the normalized probability values p′k). For example, values along the W×H dimensions of the probability array 128 represent the pixel locations for corresponding one(s) of the pixels 106, and values along the N dimension represent the probability values pk (or the normalized probability values p′k) for the corresponding one(s) of the pixels 106.
In the example of
d(i)=Σk=1Npi(k)ci(k) (Equation 6)
In example Equation 6 above, d(i) represents the metric depth value corresponding to an ith one of the pixels 106, pi(k) represents the kth probability value corresponding to the one of the pixels 106, and ci(k) represents the depth value at the kth one of the bin centers 320 corresponding to the ith one of the pixels 106. In some examples, the metric depth estimation circuitry 214 generates and/or outputs the metric depth map 104 of
In the illustrated example of
The example database 218 stores data utilized, generated, and/or obtained by the depth estimation circuitry 200. The example database 218 of
The example input interface circuitry 202 of
The example model training circuitry 204 generates and/or trains one or more example models (e.g., neural network model(s)) implemented by the depth estimation circuitry 200. For example, the model training circuitry 204 generates and/or trains an example relative depth estimation model (e.g., relative depth estimation layer(s) of the neural network model(s)) to implement the encoder-decoder architecture 110 of
Artificial intelligence (AI), including machine learning (ML), deep learning (DL), and/or other artificial machine-driven logic, enables machines (e.g., computers, logic circuits, etc.) to use a model to process input data to generate an output based on patterns and/or associations previously learned by the model via a training process. For instance, the model may be trained with data to recognize patterns and/or associations and follow such patterns and/or associations when processing input data such that other input(s) result in output(s) consistent with the recognized patterns and/or associations.
Many different types of machine learning models and/or machine learning architectures exist. In examples disclosed herein, machine learning models based on MiDaS depth estimation architectures are used. For example, the machine learning models can include a transformer-based encoder-decoder architecture (e.g., a DPT encoder-decoder architecture) as a base model (e.g., a backbone), and further include one or more metric heads (e.g., prediction heads) trained on top of the base model. While a BEiT base model is used for the MiDaS architecture in this example, one or more different base models (e.g., Swin2, Swin, EfficientNet B5, etc.) can be used instead. In general, machine learning models/architectures that are suitable to use in the example approaches disclosed herein will be convolutional neural networks (CNNs). However, other types of machine learning models could additionally or alternatively be used.
In general, implementing a ML/AI system involves two phases, a learning/training phase and an inference phase. In the learning/training phase, a training algorithm is used to train a model to operate in accordance with patterns and/or associations based on, for example, training data. In general, the model includes internal parameters that guide how input data is transformed into output data, such as through a series of nodes and connections within the model to transform input data into output data. Additionally, hyperparameters are used as part of the training process to control how the learning is performed (e.g., a learning rate, a number of layers to be used in the machine learning model, etc.). Hyperparameters are defined to be training parameters that are determined prior to initiating the training process.
Different types of training may be performed based on the type of ML/AI model and/or the expected output. For example, supervised training uses inputs and corresponding expected (e.g., labeled) outputs to select parameters (e.g., by iterating over combinations of select parameters) for the ML/AI model that reduce model error (e.g., based on a cross-entropy loss). As used herein, labelling refers to an expected output of the machine learning model (e.g., a classification, an expected output value, etc.). Alternatively, unsupervised training (e.g., used in deep learning, a subset of machine learning, etc.) involves inferring patterns from inputs to select parameters for the ML/AI model (e.g., without the benefit of expected (e.g., labeled) outputs).
In some examples disclosed herein, ML/AI models are trained using supervised learning. However, any other training algorithm may additionally or alternatively be used. In examples disclosed herein, training is performed until a targeted accuracy level is reached (e.g., >95%). Training is performed using hyperparameters that control how the learning is performed (e.g., a learning rate, a number of layers to be used in the machine learning model, etc.). In some examples, pre-trained model(s) are used. In some examples re-training may be performed. Such re-training may be performed in response to, for example, poor depth detection due to, for instance, low ambient lighting.
Training is performed using training data. In examples disclosed herein, the training data originates from reference data including images representative of different three-dimensional scenes. In some examples, multiple training datasets corresponding to different domain types can be used. For example, a first training dataset can include images representative of indoor scenes, and a second training dataset can include images representative of outdoor scenes. Because supervised training is used, the training data is labeled. For example, the training data can include domain labels representing the domain types of the corresponding images. Further, the training data includes ground truth depth values (e.g., actual and/or measured depth values) for the corresponding images. For example, the ground truth depth values can include metric depth values and/or relative depth values for respective pixels of the corresponding images. In some examples, the training data can include labels representing one or more features (e.g., locations of objects and/or edges, etc.) of the corresponding images.
Once training is complete, the model(s) are deployed for use as executable construct(s) that process an input and provide an output based on the network(s) of nodes and connections defined in the model(s). In examples disclosed herein, the model(s) are stored at one or more databases (e.g., the database 218 of
Once trained, the deployed model(s) may be operated in an inference phase to process data. In the inference phase, data to be analyzed (e.g., live data) is input to the model(s), and the model(s) execute to create an output. This inference phase can be thought of as the AI “thinking” to generate the output based on what it learned from the training (e.g., by executing the model to apply the learned patterns and/or associations to the live data). In some examples, input data undergoes pre-processing before being used as an input to the machine learning model(s). Moreover, in some examples, the output data may undergo post-processing after it is generated by the AI model to transform the output into a useful result (e.g., a display of data, an instruction to be executed by a machine, etc.).
In some examples, output of the deployed model(s) may be captured and provided as feedback. By analyzing the feedback, an accuracy of the deployed model(s) can be determined. If the feedback indicates that the accuracy of the deployed model(s) is less than a threshold or other criterion, training of updated model(s) can be triggered using the feedback and an updated training data set, hyperparameters, etc., to generate updated, deployed model(s).
Referring to
In the example of
In some examples, for a corresponding one of the metric heads 122, the metric depth estimation models include corresponding ones of the bin embeddings MLP(s) 304, the bin initialization MLP(s) 306, and the attractor selection MLP(s) 308. For example, the model training circuitry 204 trains the bin embeddings MLP(s) 304 based on the corresponding one(s) of the training datasets to output bin embeddings (e.g., the bin embeddings 312) based features of images input to the depth estimation circuitry 200. In some examples, the model training circuitry 204 trains the bin initialization MLP(s) 306 based on the corresponding one(s) of the training datasets to output initial bin center positions (e.g., the first bin centers 302A) based on initial bin embeddings (e.g., the first bin embeddings 312A). In some examples, the model training circuitry 204 trains the attractor selection MLP(s) 308 based on the corresponding one(s) of the training datasets to output attractor points (e.g., the attractors 320) based on the bin embeddings 312. In some examples, the metric depth estimation model(s) are stored in the database 218 and are accessible to the bin selection circuitry 212 of
In some examples, the model training circuitry 204 trains the classification model(s) (e.g., domain classification neural network model(s)) based on the images included in the training data and the corresponding labels representing domain types of the images. For example, the model training circuitry 204 trains the classification model(s) to output a domain type (e.g., indoor or outdoor) for images input to the encoder-decoder architecture 110 of
The example encoder circuitry 206 of
The example decoder circuitry 210 of
The example domain classification circuitry 208 of
The example bin selection circuitry 212 of
The example probability calculation circuitry 216 of
The example metric depth estimation circuitry 214 of
In some examples, the depth estimation circuitry 200 includes means for interfacing. For example, the means for interfacing may be implemented by the input interface circuitry 202. In some examples, the input interface circuitry 202 may be instantiated by programmable circuitry such as the example programmable circuitry 612 of
In some examples, the depth estimation circuitry 200 includes means for training. For example, the means for training may be implemented by the model training circuitry 204. In some examples, the model training circuitry 204 may be instantiated by programmable circuitry such as the example programmable circuitry 612 of
In some examples, the depth estimation circuitry 200 includes means for encoding. For example, the means for encoding may be implemented by the encoder circuitry 206. In some examples, the encoder circuitry 206 may be instantiated by programmable circuitry such as the example programmable circuitry 612 of
In some examples, the depth estimation circuitry 200 includes means for classifying. For example, the means for classifying may be implemented by the domain classification circuitry 208. In some examples, the domain classification circuitry 208 may be instantiated by programmable circuitry such as the example programmable circuitry 612 of
In some examples, the depth estimation circuitry 200 includes means for decoding. For example, the means for decoding may be implemented by the decoder circuitry 210. In some examples, the decoder circuitry 210 may be instantiated by programmable circuitry such as the example programmable circuitry 612 of
In some examples, the depth estimation circuitry 200 includes means for selecting. For example, the means for selecting may be implemented by the bin selection circuitry 212. In some examples, the bin selection circuitry 212 may be instantiated by programmable circuitry such as the example programmable circuitry 612 of
In some examples, the depth estimation circuitry 200 includes means for estimating. For example, the means for estimating may be implemented by the metric depth estimation circuitry 214. In some examples, the metric depth estimation circuitry 214 may be instantiated by programmable circuitry such as the example programmable circuitry 612 of
In some examples, the depth estimation circuitry 200 includes means for calculating. For example, the means for calculating may be implemented by the probability calculation circuitry 216. In some examples, the probability calculation circuitry 216 may be instantiated by programmable circuitry such as the example programmable circuitry 612 of
While an example manner of implementing the depth estimation circuitry 200 is illustrated in
Flowchart(s) representative of example machine readable instructions, which may be executed by programmable circuitry to implement and/or instantiate the depth estimation circuitry 200 of
The program may be embodied in instructions (e.g., software and/or firmware) stored on one or more non-transitory computer readable and/or machine readable storage medium such as cache memory, a magnetic-storage device or disk (e.g., a floppy disk, a Hard Disk Drive (HDD), etc.), an optical-storage device or disk (e.g., a Blu-ray disk, a Compact Disk (CD), a Digital Versatile Disk (DVD), etc.), a Redundant Array of Independent Disks (RAID), a register, ROM, a solid-state drive (SSD), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., Random Access Memory (RAM) of any type, etc.), and/or any other storage device or storage disk. The instructions of the non-transitory computer readable and/or machine readable medium may program and/or be executed by programmable circuitry located in one or more hardware devices, but the entire program and/or parts thereof could alternatively be executed and/or instantiated by one or more hardware devices other than the programmable circuitry and/or embodied in dedicated hardware. The machine readable instructions may be distributed across multiple hardware devices and/or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, the client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a human and/or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that may facilitate communication between a server and an endpoint client hardware device. Similarly, the non-transitory computer readable storage medium may include one or more mediums. Further, although the example program is described with reference to the flowchart(s) illustrated in
The machine readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a fragmented format, a compiled format, an executable format, a packaged format, etc. Machine readable instructions as described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.), etc.) or a data structure (e.g., as portion(s) of instructions, code, representations of code, etc.) that may be utilized to create, manufacture, and/or produce machine executable instructions. For example, the machine readable instructions may be fragmented and stored on one or more storage devices, disks and/or computing devices (e.g., servers) located at the same or different locations of a network or collection of networks (e.g., in the cloud, in edge devices, etc.). The machine readable instructions may require one or more of installation, modification, adaptation, updating, combining, supplementing, configuring, decryption, decompression, unpacking, distribution, reassignment, compilation, etc., in order to make them directly readable, interpretable, and/or executable by a computing device and/or other machine. For example, the machine readable instructions may be stored in multiple parts, which are individually compressed, encrypted, and/or stored on separate computing devices, wherein the parts when decrypted, decompressed, and/or combined form a set of computer-executable and/or machine executable instructions that implement one or more functions and/or operations that may together form a program such as that described herein.
In another example, the machine readable instructions may be stored in a state in which they may be read by programmable circuitry, but require addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., in order to execute the machine-readable instructions on a particular computing device or other device. In another example, the machine readable instructions may need to be configured (e.g., settings stored, data input, network addresses recorded, etc.) before the machine readable instructions and/or the corresponding program(s) can be executed in whole or in part. Thus, machine readable, computer readable and/or machine readable media, as used herein, may include instructions and/or program(s) regardless of the particular format or state of the machine readable instructions and/or program(s).
The machine readable instructions described herein can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine readable instructions may be represented using any of the following languages: C, C++, Java, C #, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc.
As mentioned above, the example operations of
“Including” and “comprising” (and all forms and tenses thereof) are used herein to be open ended terms. Thus, whenever a claim employs any form of “include” or “comprise” (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or within a claim recitation of any kind, it is to be understood that additional elements, terms, etc., may be present without falling outside the scope of the corresponding claim or recitation. As used herein, when the phrase “at least” is used as the transition term in, for example, a preamble of a claim, it is open-ended in the same manner as the term “comprising” and “including” are open ended. The term “and/or” when used, for example, in a form such as A, B, and/or C refers to any combination or subset of A, B, C such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.
As used herein, singular references (e.g., “a”, “an”, “first”, “second”, etc.) do not exclude a plurality. The term “a” or “an” object, as used herein, refers to one or more of that object. The terms “a” (or “an”), “one or more”, and “at least one” are used interchangeably herein. Furthermore, although individually listed, a plurality of means, elements, or actions may be implemented by, e.g., the same entity or object. Additionally, although individual features may be included in different examples or claims, these may possibly be combined, and the inclusion in different examples or claims does not imply that a combination of features is not feasible and/or advantageous.
As used herein, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by the connection reference and/or relative movement between those elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected and/or in fixed relation to each other. As used herein, stating that any part is in “contact” with another part is defined to mean that there is no intermediate part between the two parts.
Unless specifically stated otherwise, descriptors such as “first,” “second,” “third,” etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.” In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly within the context of the discussion (e.g., within a claim) in which the elements might, for example, otherwise share a same name.
As used herein, “approximately” and “about” modify their subjects/values to recognize the potential presence of variations that occur in real world applications. For example, “approximately” and “about” may modify dimensions that may not be exact due to manufacturing tolerances and/or other real world imperfections as will be understood by persons of ordinary skill in the art. For example, “approximately” and “about” may indicate such dimensions may be within a tolerance range of +/−10% unless otherwise specified in the below description.
As used herein “substantially real time” refers to occurrence in a near instantaneous manner recognizing there may be real world delays for computing time, transmission, etc. Thus, unless otherwise specified, “substantially real time” refers to real time+1 second.
As used herein, the phrase “in communication,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events.
As used herein, “programmable circuitry” is defined to include (i) one or more special purpose electrical circuits (e.g., an application specific circuit (ASIC)) structured to perform specific operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and/or (ii) one or more general purpose semiconductor-based electrical circuits programmable with instructions to perform specific functions(s) and/or operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include programmable microprocessors such as Central Processor Units (CPUs) that may execute first instructions to perform one or more operations and/or functions, Field Programmable Gate Arrays (FPGAs) that may be programmed with second instructions to cause configuration and/or structuring of the FPGAs to instantiate one or more operations and/or functions corresponding to the first instructions, Graphics Processor Units (GPUs) that may execute first instructions to perform one or more operations and/or functions, Digital Signal Processors (DSPs) that may execute first instructions to perform one or more operations and/or functions, XPUs, Network Processing Units (NPUs) one or more microcontrollers that may execute first instructions to perform one or more operations and/or functions and/or integrated circuits such as Application Specific Integrated Circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system including multiple types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and/or any combination(s) thereof), and orchestration technology (e.g., application programming interface(s) (API(s)) that may assign computing task(s) to whichever one(s) of the multiple types of programmable circuitry is/are suited and available to perform the computing task(s).
As used herein integrated circuit/circuitry is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system on chip (SoC), etc.
At block 404, the example depth estimation circuitry 200 extracts one or more example features from the image 102. For example, the example encoder circuitry 206 of
At block 406, the example depth estimation circuitry 200 obtains an initial feature map (e.g., the first feature map 120A) at the example bottleneck 116 of the example encoder-decoder architecture 110 of
At block 408, the example depth estimation circuitry 200 identifies an example domain type of the image 102 based on the initial feature map (e.g., the first feature map 120A). For example, the example domain classification circuitry 208 of
At block 410, the example depth estimation circuitry 200 selects one of the metric heads 122 of
At block 412, the example depth estimation circuitry 200 converts the initial feature map (e.g., the first feature map 120A) to example initial bin embeddings. For example, the example bin selection circuitry 212 executes the example bin embedding MLP(s) 304 corresponding to the selected one of the metric heads 122 based on the first feature map 120A. As a result of executing the bin embedding MLP(s) 304, the bin selection circuitry 212 determines and/or outputs the first example bin embeddings 312A corresponding to one(s) of the pixels 106 at the bottleneck 116. In some examples, the first bin embeddings 312A have a fixed dimensionality different from a dimensionality of the first feature map 120A.
At block 414, the example depth estimation circuitry 200 selects example initial bin center positions based on the initial bin embeddings. For example, the bin selection circuitry 212 executes the example bin initialization MLP(s) 306 corresponding to the second one of the metric heads 122 based on the first bin embeddings 312A. As a result of executing the bin initialization MLP(s) 306, the bin selection circuitry 212 determines and/or outputs example positions for the example bin centers 302 of
At block 416, the example depth estimation circuitry 200 selects a next one of the example decoder layers 310 of
At block 418, the example depth estimation circuitry 200 obtains one of the feature maps 120 corresponding to the selected one of the decoder layers 310. For example, the bin selection circuitry 212 obtains and/or accesses the one of the feature maps 120 generated and/or output by the decoder 114 at the selected one of the decoder layers 310.
At block 420, the example depth estimation circuitry 200 determines the example bin embeddings 312 for the selected one of the decoder layers 310. For example, the bin selection circuitry 212 executes the example bin embedding MLP(s) 304 based on the one of the feature maps 120 corresponding to the selected one of the decoder layers 310 and based on the bin embeddings 312 from a previous one of the decoder layers 310 or the bottleneck 116. As a result of executing the bin embedding MLP(s) 304, the bin selection circuitry 212 determines and/or outputs the bin embeddings 312 corresponding to one(s) of the pixels 106 at the selected one of the decoder layers 310.
At block 422, the example depth estimation circuitry 200 determines one or more example attractor points (e.g., the attractor(s) 320) for the selected one of the decoder layers 310. For example, the bin selection circuitry 212 executes the example attractor selection MLP(s) 308 based on the bin embeddings 312 for the selected one of the decoder layers 310. As a result of executing the attractor selection MLP(s) 308, the bin selection circuitry 212 determines and/or outputs positions of the attractors 320 for corresponding one(s) of the pixels 106 at the selected one of the decoder layers 310.
At block 424, the example depth estimation circuitry 200 adjusts the positions of the bin centers 302 at the selected one of the decoder layers 310 based on the attractors 320. For example, the bin selection circuitry 212 determines an adjustment value (e.g., Δci) based on the current positions of the bin centers 302 (e.g., ci) and the positions of the attractors 320 (e.g., ak) using at least one of an example inverse attractor equation (e.g., example Equation 2 above) or an example exponential attractor equation (e.g., example Equation 3 above). In some examples, the bin selection circuitry 212 determines adjusted positions of the bin centers 302 (e.g., c′i) based on the adjustment value and the current positions of the bin centers 302 using example Equation 1 above.
At block 426, the example depth estimation circuitry 200 determines whether there are additional one(s) of the decoder layers 310 to analyze. For example, in response to the bin selection circuitry 212 determining that there are one or more additional decoder layers 310 to analyze (e.g., block 426 returns a result of YES), control returns to block 416. Alternatively, in response to the bin selection circuitry 212 determining that there are no more decoder layers 310 to analyze (e.g., block 426 returns a result of NO), control proceeds to block 428.
At block 428, the example depth estimation circuitry 200 obtains the example relative depth map 118 from the example decoder 114. For example, the example decoder circuitry 210 of
At block 430, the example depth estimation circuitry 200 obtains final bin embeddings (e.g., the fifth bin embeddings 312E) from a final one of the decoder layers 310 (e.g., the fourth decoder layer 310D). For example, the decoder circuitry 210 obtains the fifth bin embeddings 312E generated and/or determined by the bin selection circuitry 212 for the fourth decoder layer 310D. In some examples, the decoder circuitry 210 combines (e.g., concatenates) the fifth bin embeddings 312E per pixel 106 with the relative depth map 118 to generate the output array 126 of
At block 432, the example depth estimation circuitry 200 determines example probability distribution parameters based on the final bin embeddings (e.g., the fifth bin embeddings 312E) and the relative depth map 118. For example, the example probability calculation circuitry 216 of
At block 434, the example depth estimation circuitry 200 calculates example bin probability values based on the probability distribution represented in the probability array 128 of
At block 436, the example depth estimation circuitry 200 calculates and/or estimates example metric depth values per pixel 106 (e.g., d (i)) based on a linear combination of the bin center positions and the bin probability values. For example, the example metric depth estimation circuitry 214 determines a linear combination of the bin array 124 (e.g., representing final positions of the bin centers 302) and the probability array 128 based on example Equation 6 above.
At block 438, the example depth estimation circuitry 200 generates, outputs, and/or stores the example metric depth map 104 corresponding to the image 102 of
At block 440, the example depth estimation circuitry 200 determines whether there are one or more additional images to analyze. For example, in response to the example input interface circuitry 202 determining that there are one or more additional images to analyze (e.g., block 440 returns a result of YES), control returns to block 402. Alternatively, in response to the example input interface circuitry 202 determining that there no more images to analyze (e.g., block 440 returns a result of NO), control ends.
The example machine-readable instructions and/or the example operations 500 of
At block 504, the example depth estimation circuitry 200 labels the reference data with indications of ground truth depth values and/or domain types. For example, the model training circuitry 204 labels the reference data to indicate the ground truth depth values (e.g., the metric depth values and/or the relative depth values) and/or the domain types (e.g., indoor or outdoor) for corresponding images represented in the data. At block 506, the example model training circuitry 204 generates training data based on the labeled data. In some examples, the model training circuitry 204 separates the training data into different training datasets corresponding to respective different domain types (e.g., an indoor training dataset and an outdoor training dataset).
At block 508, the example model training circuitry 204 trains one or more neural networks using the training data. For example, the model training circuitry 204 performs training of the neural network(s) based on supervised learning. As a result of the training, the domain classification model(s) are generated at block 510. Based on the domain classification model(s), the neural network(s) are trained to identify domain types (e.g., indoor or outdoor) of images input to the encoder-decoder architecture 110 of
The programmable circuitry platform 600 of the illustrated example includes programmable circuitry 612. The programmable circuitry 612 of the illustrated example is hardware. For example, the programmable circuitry 612 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and/or microcontrollers from any desired family or manufacturer. The programmable circuitry 612 may be implemented by one or more semiconductor based (e.g., silicon based) devices. In this example, the programmable circuitry 612 implements the example input interface circuitry 202, the example model training circuitry 204, the example encoder circuitry 206, the example domain classification circuitry 208, the example decoder circuitry 210, the example bin selection circuitry 212, the example metric depth estimation circuitry 214, the example probability calculation circuitry 216, and the example database 218.
The programmable circuitry 612 of the illustrated example includes a local memory 613 (e.g., a cache, registers, etc.). The programmable circuitry 612 of the illustrated example is in communication with main memory 614, 616, which includes a volatile memory 614 and a non-volatile memory 616, by a bus 618. The volatile memory 614 may be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and/or any other type of RAM device. The non-volatile memory 616 may be implemented by flash memory and/or any other desired type of memory device. Access to the main memory 614, 616 of the illustrated example is controlled by a memory controller 617. In some examples, the memory controller 617 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or any other type of circuitry to manage the flow of data going to and from the main memory 614, 616.
The programmable circuitry platform 600 of the illustrated example also includes interface circuitry 620. The interface circuitry 620 may be implemented by hardware in accordance with any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, a Bluetooth® interface, a near field communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, and/or a Peripheral Component Interconnect Express (PCIe) interface.
In the illustrated example, one or more input devices 622 are connected to the interface circuitry 620. The input device(s) 622 permit(s) a user (e.g., a human user, a machine user, etc.) to enter data and/or commands into the programmable circuitry 612. The input device(s) 622 can be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a trackpad, a trackball, an isopoint device, and/or a voice recognition system.
One or more output devices 624 are also connected to the interface circuitry 620 of the illustrated example. The output device(s) 624 can be implemented, for example, by display devices (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touchscreen, etc.), a tactile output device, a printer, and/or speaker. The interface circuitry 620 of the illustrated example, thus, typically includes a graphics driver card, a graphics driver chip, and/or graphics processor circuitry such as a GPU.
The interface circuitry 620 of the illustrated example also includes a communication device such as a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, and/or a network interface to facilitate exchange of data with external machines (e.g., computing devices of any kind) by a network 626. The communication can be by, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a beyond-line-of-sight wireless system, a line-of-sight wireless system, a cellular telephone system, an optical connection, etc.
The programmable circuitry platform 600 of the illustrated example also includes one or more mass storage discs or devices 628 to store firmware, software, and/or data. Examples of such mass storage discs or devices 628 include magnetic storage devices (e.g., floppy disk, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, and/or solid-state storage discs or devices such as flash memory devices and/or SSDs.
The machine readable instructions 632, which may be implemented by the machine readable instructions of
The cores 702 may communicate by a first example bus 704. In some examples, the first bus 704 may be implemented by a communication bus to effectuate communication associated with one(s) of the cores 702. For example, the first bus 704 may be implemented by at least one of an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 704 may be implemented by any other type of computing or electrical bus. The cores 702 may obtain data, instructions, and/or signals from one or more external devices by example interface circuitry 706. The cores 702 may output data, instructions, and/or signals to the one or more external devices by the interface circuitry 706. Although the cores 702 of this example include example local memory 720 (e.g., Level 1 (L1) cache that may be split into an L1 data cache and an L1 instruction cache), the microprocessor 700 also includes example shared memory 710 that may be shared by the cores (e.g., Level 2 (L2 cache)) for high-speed access to data and/or instructions. Data and/or instructions may be transferred (e.g., shared) by writing to and/or reading from the shared memory 710. The local memory 720 of each of the cores 702 and the shared memory 710 may be part of a hierarchy of storage devices including multiple levels of cache memory and the main memory (e.g., the main memory 614, 616 of
Each core 702 may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuitry. Each core 702 includes control unit circuitry 714, arithmetic and logic (AL) circuitry (sometimes referred to as an ALU) 716, a plurality of registers 718, the local memory 720, and a second example bus 722. Other structures may be present. For example, each core 702 may include vector unit circuitry, single instruction multiple data (SIMD) unit circuitry, load/store unit (LSU) circuitry, branch/jump unit circuitry, floating-point unit (FPU) circuitry, etc. The control unit circuitry 714 includes semiconductor-based circuits structured to control (e.g., coordinate) data movement within the corresponding core 702. The AL circuitry 716 includes semiconductor-based circuits structured to perform one or more mathematic and/or logic operations on the data within the corresponding core 702. The AL circuitry 716 of some examples performs integer based operations. In other examples, the AL circuitry 716 also performs floating-point operations. In yet other examples, the AL circuitry 716 may include first AL circuitry that performs integer-based operations and second AL circuitry that performs floating-point operations. In some examples, the AL circuitry 716 may be referred to as an Arithmetic Logic Unit (ALU).
The registers 718 are semiconductor-based structures to store data and/or instructions such as results of one or more of the operations performed by the AL circuitry 716 of the corresponding core 702. For example, the registers 718 may include vector register(s), SIMD register(s), general-purpose register(s), flag register(s), segment register(s), machine-specific register(s), instruction pointer register(s), control register(s), debug register(s), memory management register(s), machine check register(s), etc. The registers 718 may be arranged ina bank as shown in
Each core 702 and/or, more generally, the microprocessor 700 may include additional and/or alternate structures to those shown and described above. For example, one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more converged/common mesh stops (CMS s), one or more shifters (e.g., barrel shifter(s)) and/or other circuitry may be present. The microprocessor 700 is a semiconductor device fabricated to include many transistors interconnected to implement the structures described above in one or more integrated circuits (ICs) contained in one or more packages.
The microprocessor 700 may include and/or cooperate with one or more accelerators (e.g., acceleration circuitry, hardware accelerators, etc.). In some examples, accelerators are implemented by logic circuitry to perform certain tasks more quickly and/or efficiently than can be done by a general-purpose processor. Examples of accelerators include ASICs and FPGAs such as those discussed herein. A GPU, DSP and/or other programmable device can also be an accelerator. Accelerators may be on-board the microprocessor 700, in the same chip package as the microprocessor 700 and/or in one or more separate packages from the microprocessor 700.
More specifically, in contrast to the microprocessor 700 of
In the example of
In some examples, the binary file is compiled, generated, transformed, and/or otherwise output from a uniform software platform utilized to program FPGAs. For example, the uniform software platform may translate first instructions (e.g., code or a program) that correspond to one or more operations/functions ina high-level language (e.g., C, C++, Python, etc.) into second instructions that correspond to the one or more operations/functions in an HDL. In some such examples, the binary file is compiled, generated, and/or otherwise output from the uniform software platform based on the second instructions. In some examples, the FPGA circuitry 800 of
The FPGA circuitry 800 of
The FPGA circuitry 800 also includes an array of example logic gate circuitry 808, a plurality of example configurable interconnections 810, and example storage circuitry 812. The logic gate circuitry 808 and the configurable interconnections 810 are configurable to instantiate one or more operations/functions that may correspond to at least some of the machine readable instructions of
The configurable interconnections 810 of the illustrated example are conductive pathways, traces, vias, or the like that may include electrically controllable switches (e.g., transistors) whose state can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more of the logic gate circuitry 808 to program desired logic circuits.
The storage circuitry 812 of the illustrated example is structured to store result(s) of the one or more of the operations performed by corresponding logic gates. The storage circuitry 812 may be implemented by registers or the like. In the illustrated example, the storage circuitry 812 is distributed amongst the logic gate circuitry 808 to facilitate access and increase execution speed.
The example FPGA circuitry 800 of
Although
It should be understood that some or all of the circuitry of
In some examples, some or all of the circuitry of
In some examples, the programmable circuitry 612 of
A block diagram illustrating an example software distribution platform 905 to distribute software such as the example machine readable instructions 632 of
From the foregoing, it will be appreciated that example systems, apparatus, articles of manufacture, and methods have been disclosed that estimate metric depth values for single images. Examples disclosed herein train an example encoder-decoder architecture for relative depth estimation, and add one or more example metric heads trained for metric depth estimation. Examples disclosed herein estimate the metric depth values of corresponding pixels based on bin center positions output by the metric heads, where the metric heads utilize features output at different decoder layers of the encoder-decoder architecture to iteratively adjust and/or refine the bin center positions based. By utilizing information available at the different decoder layers (e.g., in addition to the information available at an output of the encoder-decoder architecture), examples disclosed herein improve accuracy of metric depth estimations for an image. As a result, disclosed systems, apparatus, articles of manufacture, and methods improve the efficiency of using a computing device by improving performance of downstream applications that utilize the metric depth estimations. Further, examples disclosed herein generate a metric depth estimation model that generalizes across multiple datasets and/or domains, thereby reducing utilization of memory and/or computational power of the computing device for re-training of the model. Disclosed systems, apparatus, articles of manufacture, and methods are accordingly directed to one or more improvement(s) in the operation of a machine such as a computer or other electronic and/or mechanical device.
Example methods, apparatus, systems, and articles of manufacture for monocular depth estimation are disclosed herein. Further examples and combinations thereof include the following:
Example 1 includes an apparatus comprising interface circuitry, and programmable circuitry to be programmed by instructions to at least determine bin center positions for a pixel of an image based on first features obtained at a first decoder layer of an encoder-decoder architecture, the image representative of a three-dimensional scene, the bin center positions corresponding to respective different metric depth values, adjust the bin center positions at a second decoder layer of the encoder-decoder architecture based on an attractor point, the attractor point based on the first features and second features obtained at the second decoder layer, and output a metric depth map corresponding to the image, the metric depth map including a metric depth value corresponding to the pixel, the metric depth value based on the adjusted bin center positions.
Example 2 includes the apparatus of example 1, wherein the programmable circuitry is to identify, based on the first features, a domain type corresponding to the image, and execute a neural network model corresponding to the domain type, the neural network model to output the bin center positions at the first decoder layer.
Example 3 includes the apparatus of example 2, wherein the domain type corresponds to at least one of an indoor scene or an outdoor scene.
Example 4 includes the apparatus of example 2, wherein the programmable circuitry is to train one or more first layers of the neural network based on relative depth training data, the one or more first layers including the first and second decoder layers, and train one or more second layers of the neural network model based on metric depth training data corresponding to the domain type.
Example 5 includes the apparatus of example 1, wherein the programmable circuitry is to obtain, with the encoder-decoder architecture, a relative depth value for the pixel, determine, based on the relative depth value and the second features, bin probability values corresponding to respective ones of the adjusted bin center positions, and determine the metric depth value based on a linear combination of the bin probability values and the respective ones of the adjusted bin center positions.
Example 6 includes the apparatus of example 5, wherein the programmable circuitry is to determine the bin probabilities values based on a log binomial distribution.
Example 7 includes the apparatus of example 1, wherein the first features correspond to a first dimensionality and the second features correspond to a second dimensionality different from the first dimensionality, and the programmable circuitry is to execute one or more neural network models to map the first features to first bin embeddings and map the second features to second bin embeddings, the first bin embeddings and the second bin embeddings corresponding to a third dimensionality different from the first and second dimensionalities.
Example 8 includes the apparatus of example 7, wherein the programmable circuitry is to determine the bin center positions at the first decoder layer based on the first bin embeddings, select the attractor point based on the second bin embeddings, calculate an adjustment value based on differences between the bin center positions and the attractor point, and adjust the bin center positions at the second decoder layer based on the adjustment value.
Example 9 includes a non-transitory computer readable medium comprising instructions to cause programmable circuitry to at least determine bin center positions for a pixel of an image based on first features obtained at a first decoder layer of an encoder-decoder architecture, the image representative of a three-dimensional scene, the bin center positions corresponding to respective different metric depth values, adjust the bin center positions at a second decoder layer of the encoder-decoder architecture based on an attractor point, the attractor point based on the first features and second features obtained at the second decoder layer, and output a metric depth map corresponding to the image, the metric depth map including a metric depth value corresponding to the pixel, the metric depth value based on the adjusted bin center positions.
Example 10 includes the non-transitory computer readable medium of example 9, wherein the instructions are to cause the programmable circuitry to identify, based on the first features, a domain type corresponding to the image, and execute a neural network model corresponding to the domain type, the neural network model to output the bin center positions at the first decoder layer.
Example 11 includes the non-transitory computer readable medium of example 10, wherein the domain type corresponds to at least one of an indoor scene or an outdoor scene.
Example 12 includes the non-transitory computer readable medium of example 10, wherein the instructions are to cause the programmable circuitry to train one or more first layers of the neural network based on relative depth training data, the one or more first layers including the first and second decoder layers, and train one or more second layers of the neural network model based on metric depth training data corresponding to the domain type.
Example 13 includes the non-transitory computer readable medium of example 9, wherein the instructions are to cause the programmable circuitry to obtain, with the encoder-decoder architecture, a relative depth value for the pixel, determine, based on the relative depth value and the second features, bin probability values corresponding to respective ones of the adjusted bin center positions, and determine the metric depth value based on a linear combination of the bin probability values and the respective ones of the adjusted bin center positions.
Example 14 includes the non-transitory computer readable medium of example 13, wherein the instructions are to cause the programmable circuitry to determine the bin probabilities values based on a log binomial distribution.
Example 15 includes the non-transitory computer readable medium of example 9, wherein the first features correspond to a first dimensionality and the second features correspond to a second dimensionality different from the first dimensionality, and the instructions are to cause the programmable circuitry to execute one or more neural network models to map the first features to first bin embeddings and map the second features to second bin embeddings, the first bin embeddings and the second bin embeddings corresponding to a third dimensionality different from the first and second dimensionalities.
Example 16 includes the non-transitory computer readable medium of example 15, wherein the instructions are to cause the programmable circuitry to determine the bin center positions at the first decoder layer based on the first bin embeddings, select the attractor point based on the second bin embeddings, calculate an adjustment value based on differences between the bin center positions and the attractor point, and adjust the bin center positions at the second decoder layer based on the adjustment value.
Example 17 includes an apparatus comprising bin selection circuitry to determine bin center positions for a pixel of an image based on first features obtained at a first decoder layer of an encoder-decoder architecture, the image representative of a three-dimensional scene, the bin center positions corresponding to respective different metric depth values, and adjust the bin center positions at a second decoder layer of the encoder-decoder architecture based on an attractor point, the attractor point based on the first features and second features obtained at the second decoder layer, and metric depth estimation circuitry to output a metric depth map corresponding to the image, the metric depth map including a metric depth value corresponding to the pixel, the metric depth value based on the adjusted bin center positions.
Example 18 includes the apparatus of example 17, further including domain classification circuitry to identify, based on the first features, a domain type corresponding to the image, and cause execution of a neural network model corresponding to the domain type, the neural network model to output the bin center positions at the first decoder layer.
Example 19 includes the apparatus of example 18, wherein the domain type corresponds to at least one of an indoor scene or an outdoor scene.
Example 20 includes the apparatus of example 18, further including model training circuitry to train one or more first layers of the neural network based on relative depth training data, the one or more first layers including the first and second decoder layers, and train one or more second layers of the neural network model based on metric depth training data corresponding to the domain type.
Example 21 includes the apparatus of example 17, further including probability calculation circuitry to obtain, from the encoder-decoder architecture, a relative depth value for the pixel, and determine, based on the relative depth value and the second features, bin probability values corresponding to respective ones of the adjusted bin center positions, the metric depth estimation circuitry to determine the metric depth value based on a linear combination of the bin probability values and the respective ones of the adjusted bin center positions.
Example 22 includes the apparatus of example 21, wherein the probability calculation circuitry is to determine the bin probabilities values based on a log binomial distribution.
Example 23 includes the apparatus of example 17, wherein the first features correspond to a first dimensionality and the second features correspond to a second dimensionality different from the first dimensionality, and the bin selection circuitry is to map the first features to first bin embeddings and map the second features to second bin embeddings, the first bin embeddings and the second bin embeddings corresponding to a third dimensionality different from the first and second dimensionalities.
Example 24 includes the apparatus of example 23, wherein the bin selection circuitry is to determine the bin center positions at the first decoder layer based on the first bin embeddings, select the attractor point based on the second bin embeddings, calculate an adjustment value based on differences between the bin center positions and the attractor point, and adjust the bin center positions at the second decoder layer based on the adjustment value.
Example 25 includes a method comprising determining bin center positions for a pixel of an image based on first features obtained at a first decoder layer of an encoder-decoder architecture, the image representative of a three-dimensional scene, the bin center positions corresponding to respective different metric depth values, adjusting the bin center positions at a second decoder layer of the encoder-decoder architecture based on an attractor point, the attractor point based on the first features and second features obtained at the second decoder layer, and outputting a metric depth map corresponding to the image, the metric depth map including a metric depth value corresponding to the pixel, the metric depth value based on the adjusted bin center positions.
Example 26 includes the method of example 25, further including identifying, based on the first features, a domain type corresponding to the image, and executing a neural network model corresponding to the domain type, the neural network model to output the bin center positions at the first decoder layer.
Example 27 includes the method of example 26, wherein the domain type corresponds to at least one of an indoor scene or an outdoor scene.
Example 28 includes the method of example 26, further including training one or more first layers of the neural network based on relative depth training data, the one or more first layers including the first and second decoder layers, and training one or more second layers of the neural network model based on metric depth training data corresponding to the domain type.
Example 29 includes the method of example 25, further including obtaining, with the encoder-decoder architecture, a relative depth value for the pixel, determining, based on the relative depth value and the second features, bin probability values corresponding to respective ones of the adjusted bin center positions, and determining the metric depth value based on a linear combination of the bin probability values and the respective ones of the adjusted bin center positions.
Example 30 includes the method of example 29, further including determining the bin probabilities values based on a log binomial distribution.
Example 31 includes the method of example 25, wherein the first features correspond to a first dimensionality and the second features correspond to a second dimensionality different from the first dimensionality, further including executing one or more neural network models to map the first features to first bin embeddings and map the second features to second bin embeddings, the first bin embeddings and the second bin embeddings corresponding to a third dimensionality different from the first and second dimensionalities.
Example 32 includes the method of example 31, further including determining the bin center positions at the first decoder layer based on the first bin embeddings, selecting the attractor point based on the second bin embeddings, calculating an adjustment value based on differences between the bin center positions and the attractor point, and adjusting the bin center positions at the second decoder layer based on the adjustment value.
The following claims are hereby incorporated into this Detailed Description by this reference. Although certain example systems, apparatus, articles of manufacture, and methods have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, apparatus, articles of manufacture, and methods fairly falling within the scope of the claims of this patent.