Claims
- 1. A method for organizing 2M single-bit memory cells into 2N blocks, where M is a multiplication-product of N by I by J, and N, I and J are positive integers, the method comprising steps of:
(a) dividing said 2M single-bit memory cells into N pairs with each pair includes two symmetrical blocks where each of said block includes {J(j)xI} single-bit memory cells, and where j=1, 2, 3, . . . , N, and said positive integer I representing a bit length of a stored data; (b) arranging said single-bit memory cells in each of said blocks into a J(j)-by-I two dimensional array and by connecting every I single memory cells with a first level bit line in a first bit-line direction and every J(j) single-memory cells by a first level word line wherein each said first level word lines and said first level bit lines intersect at one of said single-bit memory cells; (c) connecting each of said I first level bit lines in each of said blocks to a corresponding multiple-block first level bit-lines, i.e., multiple-block bit-line-i where i=1, 2, 3, . . . I, wherein said multiple-block first-level bit lines being arranged in a second bit-line direction different from said first-bit line direction and each being connected to a corresponding first level sense-amplifier-i where i=1, 2, 3, . . . I; (d) applying a block select signal to activate one of said J(j) first level word lines in one of said blocks, i.e., block-n where n is a positive integer ranging from 1 to N, and employing said I sense amplifiers for detecting memory-cell signals from each of said first level I bit lines of said block n and a corresponding symmetrical block of said block-n, for reading data therefrom whereby said N blocks sharing said I sense amplifiers; and (e) forming a select transistor for each of said memory cells for connecting to one of said first level word lines and applying a bias voltage on a gate of said select transistor for blocking a leakage current flowing through a channel controlled by said gate when said select transistor is in a standby mode.
- 2. A memory array unit including 2M single-bit memory cells organized into 2N blocks, where M is a multiplication-product of N by I by J, and N, I and J are positive integers, the memory array unit are operated with N first level sense amplifiers, said unit comprising:
N pairs of dual-symmetrical blocks where each of said blocks includes {J(j)xI} single-bit memory cells, and where j=1, 2, 3, . . . , N, and said positive integer I representing a bit length of a stored data; each of said blocks includes a J(j)-by-I two dimensional array and wherein every I single memory cells being connected with a first level bit line along a first bit-line direction and every J(j) single-memory cells are connected by a first level word line wherein each said first level word lines and said first level bit lines intersect at one of said single-bit memory cells; each of said I first level bit lines in each of said blocks being connected to a corresponding multiple-block first level bit-lines, i.e., multiple-block bit-line-i where i=1, 2, 3, . . . I, wherein said multiple-block first-level bit lines being arranged in a second bit-line direction different from said first-bit line direction and each being connected to said corresponding first level sense-amplifier-i where i=1, 2, 3, . . . I; a block select signal means for activating a block select signal to activate one of said J(j) first level word lines in one of said blocks, i.e., block-n where n is a positive integer ranging from 1 to N, and wherein said I sense amplifiers being activated for detecting memory-cell signals from each of said first level I bit lines of said block n and a corresponding symmetrical block of said block-n, for reading data therefrom whereby said N blocks sharing said I first level sense amplifiers; and each of said memory cells further includes a select transistor for connecting to one of said first level word lines wherein each of said word lines is connected to word line driver for applying a bias voltage on a gate of said select transistor for blocking a leakage current flowing through a channel controlled by said gate when said select transistor is in a standby mode.
- 3. A semiconductor memory device provided for operation with a plurality of first level sense-amplifiers comprising:
a memory cell array having a plurality of first-direction first-level bit lines disposed in a parallel manner along a first direction; said memory cell array further includes a plurality of word lines intersected with said first-direction first-level bit lines; said memory cell array further includes a plurality of memory cells wherein each of said plurality of memory cells being coupled between one of said first-direction first level bit lines and one of said word lines for storing data therein; a plurality of different-direction first level bit lines disposed in parallel manner along a plurality of different directions being different from said first direction, wherein each of said different-direction first level bit lines connected between a plurality of said first-direction first level bit lines and one of said first level sense amplifiers; and each of said memory cell further includes a select transistor for connecting to one of said word lines controlled by a word line driver for applying a bias voltage on a gate of said select transistor for blocking a leakage current flowing through a channel controlled by said gate when said select transistor is in a standby mode.
- 4. The semiconductor memory device of claim 3 wherein:
said word line driver further includes a word line driver circuit for applying a standby leakage-prevention-voltage lower than a substrate voltage on said gate of said select transistor for blocking said leakage current flowing via a N-channel underneath said gate when said select transistor is in a standby mode.
- 5. The semiconductor memory device of claim 3 wherein:
said word line driver further includes a word line driver circuit for applying a standby leakage-prevention-voltage higher than a substrate voltage on said gate of said select transistor for blocking said leakage current flowing via a P-channel underneath said gate when said select transistor is in a standby mode.
- 6. The semiconductor memory device of claim 3 wherein:
each of said memory cells further includes a storage transistor having a gate connected to a power supply voltage Vcc and a drain connected to a source of said select transistor; and said gate of said select transistor is connected to one of said word lines and said select transistor further having a drain connected to one of said first level bit lines.
- 7. The semiconductor memory device of claim 6 wherein:
said word line driver circuit further includes a first and a second driver transistors for receiving a word line enabling and disabling pulses respectively and said second transistor is further connected to a bias voltage source for providing said standby leakage-prevention-voltage to said word line when said word line disabling pluses are generated from said first driver transistor.
- 8. The semiconductor memory device of claim 7 wherein:
said bias voltage source provides said standby leakage-prevention-voltage lower than a substrate voltage of said select transistor for blocking said leakage current flowing via a N-channel underneath said gate of said select transistor in a standby mode.
- 9. The semiconductor memory device of claim 7 wherein:
said bias voltage source provides said standby leakage-prevention-voltage higher than a substrate voltage of said select transistor for blocking said leakage current flowing via a P-channel underneath said gate of said select transistor in a standby mode.
- 10. The semiconductor memory device of claim 6 wherein:
said word line driver circuit further includes a first and a second driver transistors for receiving a word line (WL) enabling and a WL off pulses respectively and said second transistor is further connected to a ground voltage source for coupling said standby leakage-prevention-voltage to said word line when said WL enabling pluses are turned off by said first driver transistor and said WL off pluses are turned on by said second driver transistor.
- 11. The semiconductor memory device of claim 10 wherein:
said standby leakage-prevention-voltage coupled to said word line by said word line driver circuit is lower than a substrate voltage of said select transistor for blocking said leakage current flowing via a N-channel underneath said gate of said select transistor in a standby mode.
- 12. The semiconductor memory device of claim 7 wherein:
said standby leakage-prevention-voltage coupled to said word line by said word line driver circuit is higher than a substrate voltage of said select transistor for blocking said leakage current flowing via a P-channel underneath said gate of said select transistor in a standby mode.
- 13. A method for reducing a leakage current flowing via a channel of underneath a gate in a standby mode comprising a step of:
a) applying bias voltage on said gate for blocking said leakage current flowing via said channel.
- 14. The method of claim 13 wherein:
said step (a) of applying a bias voltage on said gate is a step of applying a voltage on said gate lower than a substrate voltage for blocking said leakage current flowing via a N-channel underneath said gate.
- 15. The method of claim 13 wherein:
said step (a) of applying a bias voltage on said gate is a step of applying a voltage on said gate higher that a substrate voltage for blocking said leakage current flowing via a P-channel underneath said gate.
- 16. The method of claim 13 wherein:
said step (a) of applying a bias voltage on said gate further comprising a step of connecting said gate to a wordline for activating/deactivating an array of memory cells.
- 17. The method of claim 16 wherein:
said step (a) of applying a bias voltage on said gate further comprising a step of connecting said wordline to a decode driver for said array of memory cells for providing said bias voltage in a standby mode.
- 18. The method of claim 17 wherein:
said step of connecting said wordline to a decode driver for providing said bias voltage in a standby mode further comprising a step of connecting said wordline to a first and a second driver transistors for receiving a word line enabling and disabling pulses respectively; and connecting said second transistor to a bias voltage source for providing said standby leakage-prevention-voltage to said word line when said word line disabling pluses are generated from said first driver transistor.
- 19. The method of claim 18 wherein:
said step of connecting said second transistor to a bias voltage source is a step of connecting said second transistor to a bias voltage source for providing said standby leakage-prevention-voltage lower than a substrate voltage of said select transistor for blocking said leakage current flowing via a N-channel underneath said gate of said select transistor in a standby mode.
- 20. The method of claim 18 wherein:
said step of connecting said second transistor to a bias voltage source is a step of connecting said second transistor to a bias voltage source for providing said standby leakage-prevention-voltage higher than a substrate voltage of said select transistor for blocking said leakage current flowing via a P-channel underneath said gate of said select transistor in a standby mode.
- 21. The method of claim 17 wherein:
said step of connecting said wordline to a decode driver for providing said bias voltage in a standby mode further comprising a step of connecting said wordline to a first and a second driver transistors for receiving a word line (WL) enabling and a WL off pulses respectively; and connecting said second transistor to a ground voltage source for coupling said standby leakage-prevention-voltage to said word line when said WL enabling pluses are turned off by said first driver transistor and said WL off pluses are turned on by said second driver transistor.
- 22. The method of claim 21 wherein:
said step coupling said standby leakage-prevention-voltage to said word line is a step of coupling said standby leakage-prevention-voltage lower than a substrate voltage of said select transistor for blocking said leakage current flowing via a N-channel underneath said gate of said select transistor in a standby mode when said WL enabling pluses are turned off by said first driver transistor and said WL off pluses are turned on by said second driver transistor.
- 23. The method of claim 21 wherein:
said step coupling said standby leakage-prevention-voltage to said word line is a step of coupling said standby leakage-prevention-voltage higher than a substrate voltage of said select transistor for blocking said leakage current flowing via a P-channel underneath said gate of said select transistor in a standby mode when said WL enabling pluses are turned off by said first driver transistor and said WL off pluses are turned on by said second driver transistor.
- 24. A method for reducing a gate-drain leakage current when a transistor is turned off comprising a step of:
(a) forming a gate and a drain region for said transistor by disposing said drain region at a distance away from and has no overlapping area with a gate-oxide layer insulating said gate.
- 25. The method of claim 24 wherein:
said step of (a) disposing said drain region at a distance away from and has no overlapping area with said gate-oxide layer further comprising a step (a1l) of blocking a light-doped diffusion (LDD) implant above said drain region in manufacturing said transistor.
- 26. The method of claim 24 further comprising:
said step of (a) disposing said drain region at a distance away from and has no overlapping area with said gate-oxide layer further comprising a step (a2) of forming a spacer surrounding said gate for carrying out a drain-source implant to form said drain region at a distance away and has no overlapping area with said gate-oxide layer.
- 27. The method of claim 24 wherein:
said step of (a) disposing said drain region at a distance away from and has no overlapping area with said gate-oxide layer further comprising a step (a3) employing a special mask for performing a reverse-conductivity implant into a light-doped diffusion (LDD) region for canceling said LDD region surrounding said drain region.
- 28. The method of claim 15 wherein:
said step of (a) disposing said drain region at a distance away from and has no overlapping area with said gate-oxide layer further comprising a step (a4) of forming a spacer surrounding said gate for carrying out a drain-source implant to form said drain region at a distance away and has no overlapping area with said gate-oxide layer.
- 29. The method of claim 15 further comprising:
forming a bitline connected to said drain region.
- 30. A method for reducing an area gate leakage current when a transistor is turned on comprising a step of:
(a) connecting a gate of said transistor to a voltage Vplate wherein Vplate is lower than a full power voltage of said transistor.
- 31. The method of claim 30 wherein:
said step (a) of connecting a gate of said transistor to a voltage Vplate lower than a full power voltage is a step (a1) of connecting said gate of said transistor to a voltage Vplate wherein Vplate is about one-half of said full power voltage of said transistor.
- 32. The method of claim 31 further comprising:
connecting a drain of said transistor to a source of a select transistor and connecting said select transistor to a bit line and a word line for using said transistor as a bit-storage transistor.
- 33. A method for reducing an area gate leakage current when a transistor is turned on comprising a step of:
(a) forming said transistor as a depletion transistor for a lower voltage between a gate of said transistor and a substrate supporting said transistor.
- 34. The method of claim 33 further comprising:
connecting a drain of said transistor to a source of a select transistor and connecting said select transistor to a bit line and a word line for using said transistor as a bit-storage transistor.
- 35. A method for reducing an area gate leakage current when a transistor is turned on comprising a step of:
(a) forming said transistor as a native transistor for a lower voltage between a gate of said transistor and a substrate supporting said transistor.
- 37. The method of claim 36 further comprising:
connecting a drain of said transistor to a source of a select transistor and connecting said select transistor to a bit line and a word line for using said transistor as a bit-storage transistor.
Parent Case Info
[0001] This is a Continuous-In-Part (CIP) Application of a previously filed co-pending Application with Ser. No. 08/653,620 filed on May 24, 1996 and another co-pending application 08/805,290 filed on Feb. 25, 1997 and an International Application filed in Taiwan Intellectual Property Bureau by identical sole inventor as for this CIP Application.
Continuation in Parts (2)
|
Number |
Date |
Country |
Parent |
08653620 |
May 1996 |
US |
Child |
09753635 |
Jan 2001 |
US |
Parent |
08805290 |
Feb 1997 |
US |
Child |
09753635 |
Jan 2001 |
US |