The invention relates to apparatus for, and methods of, calculating metrics associated with a trellis representing a signal to be recovered.
In digital communication systems, Forward Error Correction (FEC) coding can be used in order to improve the reliability of the transmission link. Turbo coding schemes [C. Berrou, A. Glavieux and P. Thitimajshima, Near Shannon Limit Error-Correcting Coding and Decoding: Turbo-Codes, ICC 1993, Geneva, Switzerland, pp. 1064-1070, May 1993] belong to the family of FEC codes and are currently being used in a number of communication systems. For example, the 3GPP standard makes use of Turbo codes to help the receiver recover the transmitted information.
Turbo-codes are built from the parallel (or serial) concatenation of two (or more) constituent codes (see
In order to decode the Turbo codes with an acceptable complexity, an iterative decoding algorithm is usually selected.
For the first decoding iteration, the soft decisions corresponding to systematic bits and the soft decisions corresponding to the 1st parity bits are used by SISO decoder 10 in order to decode the first constituent code. No a priori information is used at this point since none is usually available for the first decoding iteration. The SISO decoder 10 outputs the Log Likelihood Ratios (LLRs) of the transmitted bits. The LLRs indicate how likely it is for a 0 or a 1 to have been transmitted. They are used to help the decoding performed by SISO decoder 12. However, they cannot be used directly and need to be processed so that they are in a format suitable to be input to SISO decoder 12. First, the a priori information needs to be subtracted, at 14, from the LLR, although it should be borne in mind that no a priori information is available for the first decoding iteration. This quantity formed by the difference between the LLRs and the a priori information is called extrinsic information and corresponds to the information generated by SISO decoder 10 on the transmitted bits. Moreover, these extrinsic values need to be interleaved, at 16, in order to replicate the interleaving applied at the transmitter on the sequence of bits to be coded. The decoding performed by SISO decoder 12 uses the extrinsic information generated by SISO decoder 10 with the soft decisions corresponding to the systematic bits and the soft decisions corresponding to 2nd parity bits. At the output of SISO decoder 12, a new sequence of LLRs is generated for the sequence of transmitted bits. The LLRs are used to calculate the extrinsic information generated by SISO decoder 12. After de-interleaving, this extrinsic information can be used, in subsequent decoding iterations, by SISO decoder 10 as a priori information. This decoding process is iterated a number of times so that the LLRs generated by the SISO decoders 10 and 12 are gradually improved. These refinements of the LLRs are fed to the different SISO decoding stages so that the overall decoding algorithm converges to an estimated sequence of the transmitted bits close to the MAP solution. At the end of the NTCIterations decoding iterations, the polarity of estimated transmitted bits is set according to the sign of the LLRs.
The choice of the algorithm used within the SISO decoders 10 and 12 is very important, as it will impact both the decoding performance and the complexity of the receiver. The Max-Log-MAP algorithm [W. Koch and A. Baier, Optimum and sub-optimum detection of coded data disturbed by time-varying intersymbol interference, GLOBECOM 90, pp. 1679-1684, December 1990] is one possible algorithm offering a good trade-off between performance and complexity. The case where SISO decoders 10 and 12 use the Max-Log-MAP algorithm will now be described.
It can be seen from
In
In order to calculate the LLRs, the path metrics calculated during the ‘butterflies update’ stage of the forward processing are combined with the path metrics generated during the backward processing. Hence, the path metrics generated during forward processing need to be stored in a buffer until they are used by the backward processing stage. In order to keep the receiver implementation complexity as low as possible, it is very important to minimise the size of this buffer. The number of memory bits required to store the path metrics calculated during the forward processing increases linearly with (1) the number of bits to be decoded, also referred to as code block size, (2) the number of states in the trellis representing the constituent code and (3) the number of bits required to accurately represent each path metric. The number of states in the trellis is defined by the structure of the code imposed by the transmitter and can therefore not be changed to reduce the receiver memory requirements. In order to reduce the impact of the code block size on the memory requirements, it is possible to use decoding techniques operating on windows of the received signal rather than on the whole sequence [Performance analysis of Turbo decoder for 3GPP standard using the sliding window algorithm, M. Marandian, J. Fridman, Z. Zvonar, M. Salehi, PIMRC 2001]. Finally, the number of bits required to accurately represent the results of the path metric computations should be kept as low as possible.
The operation of the SISO decoder 10 will now be described in more detail. It will be apparent that the SISO decoder 12 operates in much the same way although the interleaving of the parity samples does of course need to be taken into account.
On the transmitter side, each information bit xk is coded to generate a parity sample zk that is output alongside xk.
On the receiver side, estimates of the transmitted coded samples {{circumflex over (x)}k, {circumflex over (z)}k}kε{1, . . . , N} are first produced. The aim of the Turbo decoding architecture is to produce the LLRs of the different transmitted bits. The likelihood ratio of the kth bit can be expressed as:
The proposed Turbo decoding architecture produces scaled estimates of the logarithm value of the likelihood ratio:
The value of the parameter Lc varies with the quality of the transmission link and can be assumed to be fixed for the whole received code block.
The estimates of the LLRs of the different transmitted bits are produced by iterating a number of times the processing stages presented in
where I is the iteration number.
The various computations to be performed for the different processing stages presented in
The M forward path metrics, {tilde over (α)}km|m ε{1, . . . , M}, for the different states in the trellis corresponding to the information bit xk are calculated using the received samples {{circumflex over (x)}k−1, {circumflex over (z)}k−1} and the path metrics associated with the information bit xk−1 using the following equation:
B(j,m) denotes the trellis state going backwards in time from state m on the previous branch corresponding to input j and cj,B(j,m) denotes the parity bit corresponding to the transition leading into state m from state B(j,m).
It can be seen from the above equation that the different path metrics for the whole code block (or window if windowing techniques are being used) can be generated by processing the received samples in increasing order of k. It can also been seen from
The different metrics for the different states and all the information bits in the code block (or in the window if windowing techniques are being used) need to be stored so that they can be combined with the backward computations in order to generate the different LLRs.
The backward ‘butterflies update’ computations are very similar to the computations performed during the forward ‘butterflies update’ stage. The M backward path metrics, {tilde over (β)}km|m ε{1, . . . , M}, for the different states in the trellis corresponding to the information bit xk are calculated using the received samples {{circumflex over (x)}k, {circumflex over (z)}k} and the path metrics associated with the information bit xk+1 using the following equation:
F(j,m) denotes the trellis state going forward in time from state m on the branch corresponding to input j and Cj,F(j,m) denotes the parity bit associated with the transition from state F(j,m) into state m.
Some intermediate values created in the generation of the backward path metrics are kept so that they can be used when the forward and backward computations are combined to generate the LLRs. Those intermediate values, ({tilde over (γ)}kj,m)jε{0,1}, are computed using the following equation:
{tilde over (γ)}kj,m represents the backward metric ending in the trellis state m for an information bit j.
The backward ‘butterflies update’ computations can be simply expressed using those intermediate variables using the following equation:
For each information bit xk, the results of the current backward ‘butterflies update’ computations are combined with the stored forward path metrics so that the LLRs can be calculated using the following equation:
The a priori information for the information bit xk to be used at the next decoding iteration is calculated using the LLRs, the systematic sample and the current a priori information according to the following equation:
Note that at the last decoding iteration, this computation does not need to be performed. The decision on the transmitted bit can be performed directly using the LLRs.
According to one aspect, the invention provides a method of calculating branch metrics for a butterfly in a trellis of a MAP-genre decoding algorithm, the method comprising providing initialised branch metrics for the transitions in the butterfly and incrementing the branch metrics with a group of data values corresponding to said transitions in accordance with control signals derived from the butterfly index and one or more polynomials describing tap positions of the encoding equipment to whose operation the trellis relates, wherein said group comprises systematic bit and parity bit values.
The invention also consists in apparatus for calculating branch metrics for a butterfly in a trellis of a MAP-genre decoding algorithm, the apparatus comprising means for providing initialised branch metrics for the transitions in the butterfly and means for incrementing the branch metrics with a group of data values corresponding to said transitions in accordance with control signals derived from the butterfly index and one or more polynomials describing tap positions of the encoding equipment to whose operation the trellis relates, wherein said group comprises systematic bit and parity bit values.
The invention also relates to methods of, and apparatus for, updating state metrics in a trellis.
The proposed invention is not limited in its field of application to Turbo decoding architectures using the Max-Log-MAP algorithm. The invention can be used for receivers using any Turbo decoding architectures based on the MAP algorithm or on derived versions of the MAP algorithm.
The proposed invention can be used for both Turbo decoding receivers using windowing techniques and Turbo decoding receivers that do not use windowing techniques.
The invention may be realised in hardware, software on a processor, or a combination thereof.
By way of example only, certain embodiments of the invention will now be described with reference to the accompanying drawings, in which:
The description of the different methods forming part of the proposed invention will be made for the Turbo code defined in the 3GPP standard. Note however that the proposed techniques can be applied to any Turbo code (for example the number of constituent codes is not limited to being equal to 2 and the constraint length is not limited to 4).
An embodiment of the invention concerned with the calculation of the forward path metrics {tilde over (α)}km, the backward path metrics {tilde over (β)}km and the LLRs for SISO decoder 10 of the Turbo decoder of
A few observations on the structure of the trellis shown in
connects with the pair of ending states {(b×2), (b×2)+1}. This is the reason why the processing can be grouped in pairs of two states.
It is important to note that a given connection in a given butterfly and the same connection in another butterfly do not relate to the transmission of the same pair of information bit and parity bit values. In
It can also been seen from
The information bit χ that is associated with the upper horizontal transition in each butterfly in
B(χ,2b)=b
where b is the butterfly index value of the butterfly in question.
Then, it is possible to represent the forward metric calculations as:
and thus the need to calculate the function B is eliminated from the forward metric calculation.
The symmetries within the butterflies can then be used in order to perform the computations for the other ending state in each butterfly, as follows:
For example, for the butterfly b=0, χ=0 and cχ,0=0 in the equation for {tilde over (α)}k0 and χ=1 and cχ,0=1 in the equation for {tilde over (α)}k1.
In a similar manner,
where χ this time satisfies the equation:
F(χ,b)=2b
It will be apparent that the above equation for {tilde over (β)}kb is independent of function F. The commonality in the structures of the equations given above for {tilde over (α)}k+12b, {tilde over (α)}k+12b+1, {tilde over (β)}kb and {tilde over (β)}kb+M/2 can be exploited in the implementation of decoder 10 as will now be explained with reference to
In addition to specifying the start and end states for the butterfly that is currently being processed, the butterfly index 18 is also combined with a feedback polynomial 36 and a forward polynomial 38 in operations 40 and 42, respectively. The feedback polynomial 36 describes the position of the feedback taps in the constituent encoders of the Turbo encoding scheme that is now being decoded. Likewise, the forward polynomial describes the position of the feed-forward taps in the constituent encoders. The constituent encoders of
In operations 40 and 42, the butterfly index is combined in a bit-wise XOR operation with a respective one of the feedback and forward polynomials 36 and 38. The bits of the word r0, r1 produced by operation 40 are then XORed with one another to generate bit i0. Similarly, the bits of the word f0, f1 produced by operation 42 are XORed with one another to produce bit i1. The bits i0 and i1 are used as control inputs for process 44.
Process 44 takes as data inputs the value {circumflex over (z)}k and the value
The former value has a length Bsd bits and the latter has a length Bapp+1 bits. Process 44 allocates the branch metric values that are to be combined with the path metrics 32 and 34. In process 44, two parameters BM[0] and BM[1] are both set to 0 as an initial step. Next, BM[i0] is incremented by the value
Finally, the parameter BM[i1] is incremented by the value {circumflex over (z)}k. The values of parameters BM[0] and BM[1] produced by process 44 now represent the branch metrics that are to be combined with the retrieved forward path metrics 32 and 34. Since the number of bits require to store the sum of the sample {circumflex over (x)}k and the a priori information is larger than, or equal to, number of bits used for the parity sample {circumflex over (z)}k (i.e., Bapp>Bsd), the branch metrics are allowed a length of Bapp+2 bits.
The branch metric BM[0] that is produced by process 44 is combined with retrieved path metrics 32 and 34 in operations 46 and 48 respectively. Likewise, branch metric BM[1] produced by process 44 is combined with retrieved path metrics 32 and 34 in operations 50 and 52 respectively. In essence, the same process takes place in each of operations 46 to 52. Within each of those operations, a retrieved path metric is added to a branch metric and the result is constrained to a length of Bpm bits which is caused to saturate if the addition result overruns the maximum value attainable using Bpm bits. Operation 54 then selects the maximum of the values produced by processes 46 and 52 and operation 56 selects the maximum of the values produced by processes 48 and 50. The value selected by operation 54 is the path metric 58 of the upper end state of the current butterfly and the value selected by operation 56 is the path metric 60 of the lower end state in the current butterfly. For example, if the butterfly index is 1, then path metric 58 belongs to state 2 and path metric 60 belongs to state 3 of the trellis. The path metrics 58 and 60 are written into a path metric word 62 for time index k+1 at the correct points as dictated by the calculated end states 24. When all of the butterflies for time index k have been processed, the path metrics word 62 is written back to memory. Like path metrics word 30, path metrics word 62 is Bpm×m bits long and contains all of the forward path metrics for the states of the trellis at time index k+1 in a concatenated configuration.
In
Accordingly, the outputs of operations 46, 52, 50 and 48 have been labelled {tilde over (γ)}0 to {tilde over (γ)}3.
Since the γ values can be used to generate the LLRs on the fly, and since the backward path metrics of a stage k+1 of the trellis are only required to generate the backward path metrics of stage k of the trellis, there is no need to provide for long term storage of the backward path metrics. The backward path metrics of a given stage only need to be retained long enough to complete the calculation of the backward path metrics of the subsequent stage. Thus, in
In
In order to calculate the LLRs for the trellis stage of the end states of the backward metric butterfly that is currently being processed, the forward path metrics word 66 that was calculated earlier for that stage is retrieved. In operation 68, two forward path metrics 70 and 72 are retrieved from the forward path metrics word 66. The path metrics 70 and 72 are, respectively, the forward path metrics of the upper and lower end states of the backward path metric butterfly that is currently the subject of process 64. Operation 68 selects metrics 70 and 72 using the pair of states 22 that process 64 generates (see
Forward path metric 70 is used in operations 74 and 76 and forward path metric 72 is used in operations 78 and 80. In essence, each of operations 74 to 80 is the same and comprises the addition of one of the forward path metrics 70 and 72 with one of the values y7 to y3. In each of operations 74 to 80, the result of the addition process is constrained to a word length equal to that used for the forward path metric 70 and 72, i.e. Bpm bits. If the result produced in any of operations 74 to 80 over runs the allowed Bpm bits, then the result is saturated to the maximum result available using Bpm bits.
The allocation of the values {tilde over (γ)}0 to {tilde over (γ)}3 to the operations 74 to 80 is controlled by a switch operation 82. The switch operation 82 is controlled by the signal i0 that is produced in process 64 from the current value of the butterfly index 18 and the feedback polynomial 36 (see
The result of the subtraction process then undergoes non-linear scaling to produce the a priori information for the next iteration,
The foregoing embodiment has been described largely in terms of operations and processes. It will be understood, however, that these operations and processes can be carried out by, for example, dedicated hardware, such as an ASIC, or a general purpose data processor with appropriate software.
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0504483.9 | Mar 2005 | GB | national |
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PCT/GB2006/000652 | 2/24/2006 | WO | 00 | 7/9/2008 |
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WO2006/092564 | 9/8/2006 | WO | A |
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