Patent Application
20060054591
The disclosure relates to micro-fluid ejection assemblies and, in particular, to ejection assemblies having accurately formed flow features etched therein.
Micro-fluid ejection assemblies typically include a silicon substrate material that contains fluid openings, trenches, and/or depressions formed therein. The fluid openings, trenches, and/or depressions are collectively referred to herein as “flow features.” Such flow features may be formed by a wide variety of micromachining techniques including sand blasting, wet chemical etching and reactive ion etching. As the devices become smaller, such as for ink jet printhead applications, micromachining of the substrates becomes a more critical operation. Not all micromachining techniques are reliable enough to produce accurately placed flow features having similar flow characteristics in the substrates. Accordingly, the micro-fluid ejection assembly art is constantly searching for improved micro-fluid ejection assemblies that can be produced in high yield at a minimum cost.
One method for micromachining silicon substrates is a dry etching process such as deep reactive ion etching (DRIE) or inductively coupled plasma etching. When dry etching a silicon substrate, parameters that are beneficial to one characteristic of the etched substrate are sometimes detrimental to another characteristic of the substrate.
For example, with reference to the prior art figures of
Accordingly, there remains a need for improved structures and methods of forming fluid supply slots in a semiconductor substrate using an improved wet or dry etch process.
With regard to the above, there is provided a micro-fluid ejection assembly including a silicon substrate having a fluid supply slot therein. The fluid supply slot is formed by an etch process conducted on a substrate using, a first etch mask circumscribing a fluid supply slot location, and a second etch mask applied over a functional layer on the substrate.
In another embodiment, there is provided a method of etching a silicon substrate to provide a fluid supply slot in the substrate. The method includes applying a first etch mask over a silicon substrate. At least one fluid supply slot location is defined in the first etch mask. A second etch mask is applied over at least some regions of the substrate other than the fluid supply slot location. At least one fluid supply slot is etched through a thickness of the substrate using an etch process. The second etch mask is removed from the substrate. According to the process, the first etch mask circumscribes the fluid supply slot location.
In yet another embodiment, there is provided a micro-fluid ejection head. The micro-fluid ejection head includes a semiconductor substrate containing a plurality of micro-fluid ejection devices thereon and at least one fluid supply slot therein. The fluid supply slot has at least one edge adjacent a top side protective material. A nozzle plate is attached to the semiconductor substrate to provide the micro-fluid ejection head.
An advantage of exemplary embodiments described herein is that an etched substrate may be produced by deep reactive ion etching to provide accurately produced parts which meet or exceed critical tolerances for the parts. The parts may include a wide variety of flow features including, but not limited to, etched fluid openings or etched recesses for fluids such as inks. In particular, exemplary embodiments of the invention can reduce or eliminate delamination of a protective layer on the substrate caused by fluids attacking an undercut area of the substrate adjacent the protective layer. Top side silicon damage adjacent the fluid feed slots in the substrate may also be reduced or eliminated.
Further advantages will become apparent by reference to the detailed description of exemplary embodiments when considered in conjunction with the following drawings, in which like reference numbers denote like elements throughout the several views, and wherein:
Embodiments as described herein are particularly suitable for manufacture of semiconductor substrates for micro-fluid ejection assemblies used in fluid ejection devices. An exemplary fluid ejection device 18 is illustrated in
An exemplary ink jet printer cartridge 20 is illustrated in
The printhead 22 is attached to a printhead portion 30 of the cartridge 20. A main body 32 of the cartridge 20 includes a fluid reservoir for supply of a fluid such as ink to the printhead 22. A flexible circuit or tape automated bonding (TAB) circuit 34 containing electrical contacts 36 for connection to the printer 18 is attached to the main body 32 of the cartridge 20. Electrical tracing 38 from the electrical contacts 36 are attached to the heater chip 24 to provide activation of electrical devices on the heater chip 24 on demand from the printer 18 to which the cartridge 20 is attached. The invention however, is not limited to ink cartridges 20 as described above as the micro-fluid ejection assemblies 22 described herein may be used in a wide variety of fluid ejection devices, including but not limited to, ink jet printers, micro-fluid coolers, pharmaceutical delivery systems, and the like.
A small, cross-sectional, simplified view of a micro-fluid ejection assembly 22 is illustrated in
In order to provide electrical impulses to the heater resistor 40, the heater chip 24 undergoes a number of thin film deposition and etching steps to define multiple functional layers on a semiconductor substrate such as silicon 10 (
The first dielectric layer 46 is preferably a field oxide layer of silicon dioxide having a thickness under the resistor layer 48 of about 10,000 Angstroms. However, the first dielectric layer 46 may also be provided by other materials, including, but not limited to, silicon carbides, silicon nitrides, phosphorus spin on glass, boron doped phosphorous spin on glass, and the like. The resistor layer 48 may be selected from a wide variety of metals or alloys having resistive properties. The first and second conductive layers 50 and 60 are typically metal conductive layers. The protective layers 52, 54, and 56 include passivation materials such as SiN and SiC and tantalum.
In order to attach the nozzle plate 26 to the heater chip 24, a smoothing or planarization layer 16 is optionally applied to the heater chip 24. The planarization layer 16 may be provided by spin coating a photoresist epoxy material on the heater chip 24. A useful photoresist epoxy material for the planarization layer 16 is described, for example, in U.S. Pat. Nos. 5,907,333 and 6,193,359, the disclosures of which are incorporated herein by reference. The planarization layer 16 typically has a thickness ranging from about 1 to about 10 microns and provides passivation or protection of the heater chip 24 from corrosion from fluids which may adversely affect functional layers on the heater chip 24 such as the conductive and resistive layers 50, 60, and 48.
For simplification purposes, the layers 46-60 on the substrate 10 are collectively referred to as functional layers 64. The functional layers 64 are protected by the planarization layer 16 as shown in
The etch mask 66 should be substantially removable from the underlying planarization layer 16 without substantially affecting the planarization layer 16. Accordingly, one material for etch mask 66 is a soft mask material such as a positive or negative photoresist material. As described above, use of a conventional etch mask may result in top silicon damage 14 (
The extent and severity of top silicon damage 14 and undercutting of the planarization layer 16 varies from wafer to wafer and from slot to slot 12. Usually top silicon damage 14 is area selective, tending to be most prominent at outer edges of a wafer with gradual reduction in magnitude toward a center of the wafer. Without desiring to be bound by theory, it is believed that a plasma sheath used in dry etching is non-uniform as a result of electromagnetic field line differences from the center to the edge of the wafer. Ion trajectories in the center of the wafer are more likely to be perpendicular to the wafer, where the sheath is typically more uniform, while ion trajectories near the edge of the wafer are typically angles. Accordingly, the foregoing damage 14 and ledge 70 are more pronounced on silicon substrates near the edge of the wafer.
In order to reduce or eliminate top silicon damage 14 and delamination of the planarization layer 16 from the functional layers 64 and silicon substrate 10, a plurality of etch masks can be used. In a first embodiment, as shown in
Next, a second etch mask 66 is applied over (e.g., to a surface of) the planarization layer 16, the first etch mask 80, and into groove 82 thereby protecting the first etch mask 80, groove 82, and planarization layer 16, if present, during the dry etching process. The second etch mask 66 may be provided by a soft mask material as described above with reference to
Once the slot 12 is formed through the thickness of the substrate 10, the second etch mask 66 is removed from the heater chip 24 by conventional mask removal methods such as dissolving, etching, ashing, and the like. Since the planarization layer 16 does not extend to the top side 84 of the substrate adjacent the fluid supply slot 12, even if there is minor undercutting of the first mask 80, it is less likely that fluid will reach the planarization layer 16 and cause delamination of the layer 16 from the substrate 10.
In other embodiments, a hard etch mask 86 and a soft etch mask 66 are applied over the heater chip 24, and planarization layer 16, respectively. In a second embodiment, the soft etch mask 66 is applied over a hard etch mask 86 as well as over the planarization layer 16. As with the first etch mask 80, the hard etch mask 86 is adjacent to and substantially circumscribes the fluid supply slot location 68. During a dry etch process both the hard mask 86 and soft mask 66 recede from the fluid supply slot 12. However, as before, a portion of the hard mask 86 may remain on the substrate 10 circumscribing the fluid supply slot 12.
Suitable materials for the hard etch mask 86 include, but are not limited to, silicon dioxide, silicon carbide, silicon nitride, and silicon oxynitride. Of the foregoing, silicon dioxide is particularly preferred as the hard mask 86. A silicon oxide hard mask 86 may be provided on a surface of the substrate 10 as by growing a silicon oxide layer by exposing the substrate 10 to the atmosphere for a period of time. The thickness of the hard mask 86 may range from about 0.5 to about 5 microns. For purposes of the disclosure, references to “silicon oxide” are intended to include, silicon mono-oxide, silicon dioxide and SiOx wherein x ranges from about 1 to about 4.
A benefit of using a hard mask 86, for example silicon dioxide, is that silicon dioxide dry etches at a much slower rate than silicon. In general, silicon etches in a DRIE chamber at a rate that is about 150 to about 200 times faster than the dry etch rate of silicon dioxide. Accordingly, the hard mask 86 resists lateral etching of the substrate 10 at a top side 84 of the substrate adjacent the fluid supply slot 12 thereby reducing top side damage 14.
A disadvantage of using a hard mask 86, such as silicon dioxide, without also using the soft mask 66, is that the hard mask 86 is much more difficult to remove from the heater chip 24 and planarization layer 16 than the soft mask 66. However, the hard mask 86 recedes from the top side 84 adjacent the fluid supply slot 12 more slowly than does the soft mask 66, thereby reducing exposure of the top side 84 to reactive ion etching. Accordingly, judicious use of the hard mask 86 circumscribing a region adjacent fluid feed slot location 68 in combination with the soft mask 66 applied over regions of the substrate excluding the fluid supply slot location 68 may significantly reduce the top side damage 14 and undercutting of the planarization layer 16 described above.
Once etching of the substrate 10 is complete, any remaining soft mask 66 may be removed from the hard mask 86 and planarization layer 16 as described above. Since the planarization layer 16 does not extend to the side 84 the substrate adjacent the fluid supply slot 12, even if there is minor undercutting of the hard mask 86, it is less likely that fluid will reach the planarization layer 16 and cause delamination of the layer 16 from the substrate 10.
In third embodiment, a different combination of hard mask 88 and soft mask 90 are illustrated in
Once the slot 12 is formed through the thickness of the substrate 10, the soft mask 90 is removed as described above. As in the previous embodiment, a portion of the hard mask 88 may remain adjacent the fluid supply slot 12 as shown in
In yet another embodiment, illustrated in
While specific embodiments of the disclosure have been described with particularity herein, it will be appreciated that modification and additions by those skilled in the art may be applied to the disclosed embodiments within the spirit and scope of the appended claims.
