The miniaturization of fluid circuits is a field that has received considerable renewed interest in recent years. They were first developed for logic devices before the advent of solid state semiconductors and examples are U.S. Pat. No. 3,495,604 and U.S. Pat. No. 3,495,608. Here the logic and their interconnects are formed in a single surface of a single layer and sealed by a gasket or the backside of a further layer. More recently there has been renewed interest, particularly for the miniaturization of the analysis of fluids, thereby reducing sample size and enabling the possibility of using disposable analysis slides similar to credit cards mounted into point-of-use equipment. What has received less interest is the use of microfluidics for the manufacture of emulsions, polymer beads and the like whereby synthesis on the micro or nano-scale can be duplicated by massive parallelism to produce commercial quantities. There are many potential advantages including the mass production process being exactly the same as the research process and the possibility of extremely thorough mixing e g. to make an emulsion, without large energy inputs.
An example of manufacturing approach for multilayer microfluidics is shown at ENMA490 Fall 2003 University of Maryland to be found at:
http://www.mne.umd.edu/ugrad/courses/490 materials design/490 fall 2 003/enma490 fall2003 final project results/final-report-enma490-fall2003.pdf
This described a three dimensional interconnect structure with interconnects on two levels and vias in an intermediate level formed by moulding using PDMS and SU8 layers stacked onto a silicon wafer. This is an example of a strategy to use a base material such as silicon or glass that perhaps have certain desirable properties (e.g. toughness, cheapness, flatness) and then to add layers or selectively coat them with thin coatings or layers.
Another approach is to use a substrate of the desired material as in GB2395357A. Here a fluorinated polymer substrate is made and plasma etched to form structures. This is based on the semiconductor wafer model wherein a silicon wafer is used to form silicon devices. Whilst this approach ensures material integrity there are many problems with processing a polymer substrate. Another related approach is to form the structures in a base such as silicon and subsequently to coat their surfaces in such a way as to add surfaces that meet the requirements of the devices and interconnect layer surfaces in contact with the fluid(s) such as by coating with a fluorinated polymer. There are numerous problems associated with this approach, not least that coating a non-planar surface with well adhering, high quality and consistent thicknesses is presently difficult or impossible.
The Applicants have appreciated that one more desirable manufacturing strategy is to use a prelaminated substrate and further laminate to form active device layers separated from interconnect levels, formed in a separate layer from the devices, and connect the devices to the interconnects by means of vias. For higher densities of devices stacking of multiple device levels and interconnect levels can be achieved to provide a compact and convenient high throughput array of large numbers of microfluidic devices.
It should further be understood that fluidic devices are extremely sensitive to surfaces including such characteristics as their energy level, smoothness/roughness, shape etc. The materials used should in most cases at least not contaminate the fluid(s) (unless desired), should be long lasting and preferably be standard materials that are already approved by regulatory authorities. So, for example the Applicants prefer Food and Drug Administration (FDA) approved materials for construction rather than easy to work materials that may then need coating to meet FDA or equivalent authority approval. It may however be desired to modify surfaces at least selectively to create turbulence, enable attachment of a functional component or in some way add or create functionality to the device.
The Applicants propose manufacturing or selecting a pre-manufactured substrate that consists of a laminate. This laminate consists of planar layers with significantly different properties with respect to a patterning process such as plasma etching. Some of the layer(s) may be either sacrificial and/or some may not materially contact the fluid(s) and therefore do not need to have desirable properties with respect to the fluid(s).
Processes well known e.g. to semiconductor wafer manufacture may be used to pattern devices in one face (upper) of the laminate and interconnect structures in another (lower) face. A gasket layer is then formed that may be a separate layer or part of the same laminate. Laminates are then stacked upon each other with an interposing gasket layer such that an upper device layer faces a lower interconnect layer with a gasket layer defining interconnects between the two.
It should be understood that a gasket layer can lie within the laminate between an upper and lower level of the same laminate.
Thermal management of the process fluids within micro-fluidic devices is particularly applicable to polymeric substrates because of the low thermal conductivity of these materials. This at first seems counter-intuitive, but it is the low thermal conductivity which allows separate regions of a device to be maintained at different temperatures without excessively large heat fluxes. For example this concept would not be applicable to silicon-based devices. Although the heat exchanger structures described below would function on a silicon or glass based device, it would not be practicable to maintain separate regions of the same substrate at different temperatures.
The selection of hard mask layers that form part of the laminate that enable the successful processing of suitable materials for fluidic applications may be important. A preferable hard mask is conductive to enable electrostatic clamping to enable substrate backside pressurization to improve thermal conductivity to a thermally controlled substrate chuck.
The plasma etching of fluorinated polymers requires considerable ion bombardment as is described in GB2395357 and this creates heat that is not readily dissipated in a polymer substrate. The result is either melting of the polymer substrate, or much lower applied power levels resulting in a slow etch.
Electrostatic clamping without a conductive layer at the back or close to the back of the substrate is impossible and even mechanical clamping is of limited benefit as the heat input is from the plasma on the front face of the substrate and heat dissipation is largely from the back of the substrate to a chuck. Even running the chuck at extremely low temperatures is of limited value. GB'357 describes cryogenic cooling of a chuck, but without effective clamping of substrate to chuck and with a large thickness of polymer from front to back of the substrate, effective cooling is poor. Unfortunately the polymer has to be of a certain minimum thickness to have sufficient rigidity to remain flat and be handled. If the substrate is too thin it will not be flat and will therefore have even worse thermal conductivity to the cooled chuck and plasma processing is practically impossible.
Thus the Applicants may use a laminated substrate consisting in conductive and insulating polymer layers of less that 5 mm total thickness, preferably 3 mm or less thick and most preferable about 1.6 mm is selected. A suitable laminate is a PTFE microwave circuit board with metal, such as copper or nickel, on either or preferably both faces. To form devices on one face that face is patterned and etched as is well known in the art, preferably using the metal as a hard mask. The opposing face is patterned and etched with interconnecting structures.
It is then possible to pattern and etch vias connecting the devices on the one face to the interconnect structures on the other face, preferably from the interconnect side such that the substrate itself between device side and interconnect side is a gasket layer. Galleries through the substrate can also be formed that will interconnect the interconnect layers of stacks of substrates. Additionally or alternatively a gasket layer is formed and interposed between an upper and lower face of two substrates. Preferably this gasket layer is bonded to at least an upper or lower face of a substrate either before or after holes are formed in it that selectively connect devices to interconnect structures.
The devices and interconnects may be etched into the thickness of material and the etch process terminated by reference to time or an end-point signal. This endpoint may be achieved and etching slowed or terminated by using a laminate including a buried layer or layers that function as ‘etch stop’ layers. If such an etch-stop layer is used, this layer can remain or be (at least in part) removed by any suitable wet or dry process prior to use of the completed substrate. The selection of whether this ‘etch-stop’ layer remains is made on the basis of its suitability for the fluid it may be in contact with and the end application for the device. Reference may be made to lists of approved materials produced by relevant agencies, surface energy, fouling, leaching, absorption and in fact any relevant characteristic.
Devices may advantageously be laid out in vast numbers by using standard cell design rules as developed in the integrated circuit industry and it is therefore possible to package large numbers of active devices such as emulsifiers, mixers etc. onto a substrate. For example, with vias of 100×200 microns and a cell size of 200×600 microns with 2 emulsifiers per cell, 500,000 T branch emulsifier devices can be packaged onto a 200 mm substrate.
Suitable polymers for laminate layers and/or gasket layers include PTFE (PFA and FEP) as are supplied by DuPont including Teflon® and other polymers and metals that are generally considered to be ‘inert’ i.e. are inert enough for this application and service lifetime.
Conveniently PTFE is available bonded to metals including Nickel (both materials being Federal Drugs Administration approved) and copper from multilayer microwave circuit board suppliers such as Rogers Corp. This provides a relatively low cost, low risk route to enable the development of new structures.
A process flow may consist of the following:
A preferred process sequence may be as follows:
This second sequence may be preferable because it retains a copper conductor on the laminate (thereby enabling electrostatic clamping) for all dry etch processes.
The bonding may be by any suitable method including melting or cementing. In particular PTFE may be cemented (if treated) or thermally bonded.
There is a risk that during bonding the etched features may be at least partially filled by cement or melted material during the bonding process. This problem may be addressed by filling the etched structures with a sacrificial filler such as a soluble material before bonding and then dissolving out afterwards to ensure the bonding process does not fill the etched features.
Thus from one aspect the invention consists in a microfluidic structure having physically distinct layers including a first layer containing an active fluidic device, a second layer including at least one interconnect channel for interconnecting the device to a fluid source and/or outlet and/or another device and an intermediate layer for defining at least one via defining a fluid passageway between the device and the interconnect channel.
Preferably the structure further includes a plurality of devices in the first layer and a corresponding plurality of vias in the immediate layer. Further the structure may include a gallery passing through the interconnect channel for connecting the channel to other channels and/or a fluid source and for a fluid outlet.
The first and second layers may be formed of etchable polymer such as a fluorinated polymer or other suitable polymers can be used which can be otherwise patterned or can be imprint, moulded or otherwise shaped.
At least one of the first and second layers may include a labyrinth structure to enable local heating or cooling of a working fluid flowing through the structure. The labyrinth may be formed in part of an interconnect channel.
From a further aspect the invention consists in a microfluidic system including a stack of structures as defined above. In that case the stack may include a stack of planar elements having respective opposed faces with at least one interconnect channel in one of its faces and at least one device in the other of its faces, the elements being stacked with intermediate layers between them, so as to form the stack of structures. In an alternative embodiment the system may include a stack of planar elements having opposed faces wherein a first set of elements having at least one device formed in each of their faces and a second set of at least one interconnect channel formed in each of its faces, the elements from each set being stacked alternatively with intermediate layers between them so as to form the stack of structures.
From a still further aspect the invention includes a microfluidic element having a planar body with opposed faces and having one of the following combination of formations formed in its respective faces:
From a still further aspect the invention includes a microfluidic apparatus including cartridges containing a plurality of structures as defined above, in which case the structures may form systems as defined above.
From a yet further aspect the invention consists in a microfluidic element having opposed faces including formations in each opposed face wherein the formations are of one of the following combinations:
The substrate may initially be formed by a central etchable polymer layer with a metal layer on each of its opposed faces. In the method a first one of the metal layers may be patterned to form a hard mask and the associated face etched there through. Subsequently the substrate may be inverted and the second metal layer may be patterned and etched there through. The metal layers may be removed after etching.
It is particularly preferred that a metal layer is retained until all dry etching polymer is complete to allow electrostatic clamping of the substrate during the dry etch steps.
The method may further include drilling a gallery through at least one interconnect channel when such has been formed.
The substrate may include a central etch stop layer, which may be metal. The substrate may be formed of a fluorinated polymer.
The substrate may be patterned by alternate means to dry etching e.g. by embossing, moulding, selective curing/cross linking, ablation by laser, grit or water and the like and any other practicable method.
From a still further aspect the invention consists in a method of forming a microfluidic system including forming stacks of elements formed by any one of the methods set out above such that the face containing an interconnect channel faces a face containing a device except at the top and bottom of the stack and bonding via containing layers between them so that each device is connected to a facing interconnect channel by a via.
Prior to bonding the etching formations may be filled with removable, for example dissolvable, filler and the filler may be removed subsequent to bonding. This prevents the etched formations becoming blocked by the bonding material.
Although the invention has been defined above it is to be understood that it includes any inventive combination of the features set out above or in the following description.
The invention may be performed in various ways and specific embodiments will now be described, by way of example, with reference to the accompany drawings, in which:
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The length of the heat exchanger required for a particular application will depend upon the temperature difference between the incoming fluids, the required temperature change in the product fluid, in addition to the flow-rate and specific heat capacity of the fluids. Useful devices could be made with lengths ranging from the order of 10× to several 100× the depth of the micro-channel. The device shown has a length of approximately 1700 um.
A further enhancement would be to run coolant ducts along both sides of the product fluid duct. This would approximately double the heat transfer rate to or from the product fluid.
Coolant fluid could be any liquid or gas. However water is preferred because of its low viscosity, high specific heat capacity and absence of toxicity and similar product compatibility issues.
Obviously, the heat exchanger can be used to either raise or lower the temperature of a product or supply fluid as required. An example application is the thermally induced solidification of a droplet into a bead in the output fluid.
As before, the detail design of the structure would depend on the flow rate and specific heat capacity of the product fluid and the required temperature changes. Other functionally equivalent (non-serpentine) layouts are possible and again double sided arrangements are conceivable.
More generally, thermal zones can be generated on the substrate by means of heat exchangers as is shown in
A development of the heat exchanger principle is to engineer thermal distribution throughout an entire micro-fluidic substrate by means of single or multiple coolant circuits. If one or more reactants are required to be maintained at a first temperature prior to reaction and the product maintained at a second temperature during or after reaction, then this can be achieved by means of routing coolant ducts adjacent to the process fluid ducts so as to maintain differential temperatures within the substrate. This can be achieved using either the single layer or multiple-layer structures, or a combination thereof.
Variations on the theme are conceivable. More than two zones of temperature control could be provided by means of additional coolant circuits. The detail design of the heat transfer zone in duct 24 above duct 26 could utilise a serpentine path, or run parallel, or be arranged in some other equivalent manner, according to the detail design requirement for thermal transfer. A similar result could also be achieved using parallel ducts in a single-layer implementation.
Number | Date | Country | Kind |
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0508488.4 | Apr 2005 | GB | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/GB2006/001492 | 4/25/2006 | WO | 00 | 3/19/2008 |
Number | Date | Country | |
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60674710 | Apr 2005 | US |